From WikiChip
Difference between revisions of "cavium/octeon/cn3830-500bg1521-exp"
m (Bot: change package to new layout) |
m (Bot: corrected param) |
||
Line 10: | Line 10: | ||
| model number = CN3830-500 EXP | | model number = CN3830-500 EXP | ||
| part number = CN3830-500BG1521-EXP | | part number = CN3830-500BG1521-EXP | ||
− | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Networking | | market = Networking | ||
| first announced = August 22, 2005 | | first announced = August 22, 2005 |
Revision as of 17:58, 30 June 2017
Template:mpu The CN3830-500 EXP is a 64-bit quad-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache
- Main article: cnMIPS § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
Memory controller
![]() |
Integrated Memory Controller
|
|||||||||||||||
|
Expansions
![]() |
Expansion Options
|
|||||||||||||||
|
Networking
![]() |
Networking
|
|||||||
|
Hardware Accelerators
[Edit/Modify Accelerators Info]
![]() |
Hardware Accelerators
|
|||||||||||||||||
|
Block diagram
Datasheet
Facts about "CN3830-500 EXP - Cavium"
has ecc memory support | true + |
has hardware accelerators for data compression | true + |
has hardware accelerators for data decompression | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for regular expression | true + |
has hardware accelerators for tcp packet processing | true + |
l1$ size | 160 KiB (163,840 B, 0.156 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-800 + |