From WikiChip
Difference between revisions of "intel/xeon e3/e3-1220 v6"
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
|||
Line 1: | Line 1: | ||
{{intel title|Xeon E3-1220 v6}} | {{intel title|Xeon E3-1220 v6}} | ||
{{mpu | {{mpu | ||
− | | name | + | |name=Xeon E3-1220 v6 |
− | | no image | + | |no image=Yes |
− | + | |designer=Intel | |
− | + | |manufacturer=Intel | |
− | + | |model number=E3-1220 v6 | |
− | | designer | + | |part number=CM8067702870812 |
− | | manufacturer | + | |part number 2=BX80677E31220V6 |
− | | model number | + | |s-spec=SR329 |
− | | part number | + | |market=Workstation |
− | | part number 2 | + | |market 2=Server |
− | | s-spec | + | |first announced=March 28, 2017 |
− | | market | + | |first launched=March 28, 2017 |
− | | market 2 | + | |release price=$193 |
− | | first announced | + | |family=Xeon E3 |
− | | first launched | + | |series=E3-1200 v6 |
− | + | |locked=Yes | |
− | + | |frequency=3,000 MHz | |
− | | release price | + | |turbo frequency1=3,500 MHz |
− | + | |bus type=DMI 3.0 | |
− | | family | + | |bus rate=8 GT/s |
− | | series | + | |clock multiplier=30 |
− | | locked | + | |isa=x86-64 |
− | | frequency | + | |isa family=x86 |
− | + | |microarch=Kaby Lake | |
− | | turbo frequency1 | + | |platform=Greenlow |
− | + | |chipset=Sunrise Point | |
− | + | |chipset 2=Union Point | |
− | + | |core name=Kaby Lake DT | |
− | | bus type | + | |core family=6 |
− | + | |core stepping=B0 | |
− | | bus rate | + | |process=14 nm |
− | + | |technology=CMOS | |
− | | clock multiplier | + | |word size=64 bit |
− | + | |core count=4 | |
− | + | |thread count=4 | |
− | | isa | + | |max cpus=1 |
− | | isa | + | |max memory=64 GiB |
− | | microarch | + | |v core min=0.55 V |
− | | platform | + | |v core max=1.52 V |
− | | chipset | + | |tdp=72 W |
− | | chipset 2 | + | |tstorage min=-25 °C |
− | | core name | + | |tstorage max=125 °C |
− | | core family | + | |package module 1={{packages/intel/lga-1151}} |
− | + | |turbo frequency=Yes | |
− | | core stepping | ||
− | |||
− | | process | ||
− | |||
− | | technology | ||
− | |||
− | |||
− | |||
− | | word size | ||
− | | core count | ||
− | | thread count | ||
− | | max cpus | ||
− | | max memory | ||
− | |||
− | |||
− | | v core min | ||
− | | v core max | ||
− | |||
− | | tdp | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | | tstorage min | ||
− | | tstorage max | ||
− | |||
− | |||
− | |||
− | | package module 1 | ||
}} | }} | ||
'''Xeon E3-1220 v6''' is a {{arch|64}} [[quad-core]] [[x86]] workstation/entry server microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The E3-1220 v6 operates at 3 GHz with a TDP of 72 W supporting a {{intel|Turbo Boost}} frequency of 3.5 GHz. The processor supports up to 64 GiB of dual-channel DDR4-2400 ECC memory. This model has no integrated graphics processor. | '''Xeon E3-1220 v6''' is a {{arch|64}} [[quad-core]] [[x86]] workstation/entry server microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The E3-1220 v6 operates at 3 GHz with a TDP of 72 W supporting a {{intel|Turbo Boost}} frequency of 3.5 GHz. The processor supports up to 64 GiB of dual-channel DDR4-2400 ECC memory. This model has no integrated graphics processor. |
Revision as of 03:30, 27 June 2017
Template:mpu Xeon E3-1220 v6 is a 64-bit quad-core x86 workstation/entry server microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The E3-1220 v6 operates at 3 GHz with a TDP of 72 W supporting a Turbo Boost frequency of 3.5 GHz. The processor supports up to 64 GiB of dual-channel DDR4-2400 ECC memory. This model has no integrated graphics processor.
Cache
- Main article: Kaby Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Expansions
Expansion Options
|
||||||||
|
Graphics
This processor has no integrated graphics processor.
Features
[Edit/Modify Supported Features]
Facts about "Xeon E3-1220 v6 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1220 v6 - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology + and OS Guard + |
has intel enhanced speedstep technology | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | DDR3L-1866 + and DDR4-2400 + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |