From WikiChip
Difference between revisions of "amd/ryzen threadripper/1920x"
< amd‎ | ryzen threadripper

Line 40: Line 40:
 
}}
 
}}
 
'''Ryzen Threadripper 1920X''' is a {{arch|64}} [[dodeca-core]] high-performance [[x86]] desktop [[microprocessor]] set to be introduced by [[AMD]] in mid-[[2017]]. The 1920X, which is based on their {{amd|Zen|Zen microarchitecture|l=arch}}, is fabricated on a [[14 nm process]]. The 1920X operates at a base frequency of 3.2 GHz with a [[TDP]] of 125 W and a {{amd|Precision Boost|Boost}} frequency of 3.8 GHz. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory.
 
'''Ryzen Threadripper 1920X''' is a {{arch|64}} [[dodeca-core]] high-performance [[x86]] desktop [[microprocessor]] set to be introduced by [[AMD]] in mid-[[2017]]. The 1920X, which is based on their {{amd|Zen|Zen microarchitecture|l=arch}}, is fabricated on a [[14 nm process]]. The 1920X operates at a base frequency of 3.2 GHz with a [[TDP]] of 125 W and a {{amd|Precision Boost|Boost}} frequency of 3.8 GHz. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory.
 +
 +
 +
{{unknown features}}
 +
 +
== Cache ==
 +
{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}
 +
{{cache size
 +
|l1 cache=1.125 MiB
 +
|l1i cache=768 KiB
 +
|l1i break=12x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=384 KiB
 +
|l1d break=12x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=6 MiB
 +
|l2 break=12x512 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=32 MiB
 +
|l3 break=4x8 MiB
 +
|l3 desc=16-way set associative
 +
}}

Revision as of 01:33, 27 June 2017

Template:mpu Ryzen Threadripper 1920X is a 64-bit dodeca-core high-performance x86 desktop microprocessor set to be introduced by AMD in mid-2017. The 1920X, which is based on their Zen microarchitecture, is fabricated on a 14 nm process. The 1920X operates at a base frequency of 3.2 GHz with a TDP of 125 W and a Boost frequency of 3.8 GHz. This MPU supports up to 128 GiB of quad-channel DDR4-2666 ECC memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.125 MiB
1,152 KiB
1,179,648 B
L1I$768 KiB
786,432 B
0.75 MiB
12x64 KiB4-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  12x512 KiB8-way set associativewrite-back
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  4x8 MiB16-way set associative 
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/ryzen_threadripper/1920x&oldid=48147"
Facts about "Ryzen Threadripper 1920X - AMD"
RDF feed
l1$ size1,152 KiB (1,179,648 B, 1.125 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description4-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description8-way set associative +
l2$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +