From WikiChip
Difference between revisions of "amd/k6-2/k6-2-233afr"
m (Bot: corrected mem) |
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
||
Line 46: | Line 46: | ||
| max memory = 4 GiB | | max memory = 4 GiB | ||
− | + | ||
| power = 13.5 W | | power = 13.5 W | ||
| v core = 2.2 V | | v core = 2.2 V |
Revision as of 22:13, 23 June 2017
Template:mpu K6-2/233AFR was a 32-bit x86 K6-2-based microprocessor designed and manufactured in 1998 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 233 MHz with a FSB of 66 MHz consumed 13.5 W.
Cache
- Main article: K6-2 § Cache
L2$ can be 512 KiB to 2 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
Cache Info [Edit Values] | ||
L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
Facts about "K6-2/233AFR - AMD"
l1d$ description | 2-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |