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Difference between revisions of "intel/xeon d/d-1577"
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Revision as of 05:50, 23 June 2017

Template:mpu The Xeon D-1577 is a 64-bit hexadeca-core x86-64 microserver SoC that was introduced by Intel in February of 2016. The D-1577 operates at 1.3 GHz with a turbo frequency of 2.1 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 45 W and can support up to 128 GB of RAM (DDR3L/DDR4).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 512 KiB
524,288 B
0.5 MiB
16x32 KiB 8-way set associative (per core)
L1D$ 512 KiB
524,288 B
0.5 MiB
16x32 KiB 8-way set associative (per core)
L2$ 4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16x256 KiB 8-way set associative (per core)
L3$ 24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
16x1.5 MiB (per core)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133
Controllers 1
Channels 2
ECC Support Yes
Max memory 128 GiB

Expansions

Template:mpu expansions

Networking

Networking
SFI interface Yes
KR interface Yes
KR4 interface No
KX interface Yes
KX4 interface No
10Base-T No
100Base-T No
1000Base-T Yes
10GBase-T Yes

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-1577&oldid=46985"
Facts about "Xeon D-1577 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description8-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +