Semiconductor & Computer Engineering
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Difference between revisions of "pezy/pezy-scx/pezy-sc3"
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{{pezy title|PEZY-SC3}} | {{pezy title|PEZY-SC3}} | ||
| + | {{mpu | ||
| + | |future=Yes | ||
| + | |name=PEZY-SC3 | ||
| + | |no image=Yes | ||
| + | |designer=PEZY | ||
| + | |manufacturer=TSMC | ||
| + | |model number=PEZY-SC3 | ||
| + | |market=Supercomputer | ||
| + | |first announced=2016 | ||
| + | |first launched=2018 | ||
| + | |frequency=1,333 MHz | ||
| + | |process=7 nm | ||
| + | |technology=CMOS | ||
| + | |die area=700 mm² | ||
| + | |core count=8,096 | ||
| + | |power=400 W | ||
| + | |v core=0.65 V | ||
| + | }} | ||
'''PEZY-SC3''' ('''PEZY Super Computer 3''') is fourth generation [[many-core microprocessor]] planned by [[PEZY]]. The SC3 is planned to have at least 8192 cores, twice as many cores as its predecessor. | '''PEZY-SC3''' ('''PEZY Super Computer 3''') is fourth generation [[many-core microprocessor]] planned by [[PEZY]]. The SC3 is planned to have at least 8192 cores, twice as many cores as its predecessor. | ||
Revision as of 05:05, 23 June 2017
Template:mpu PEZY-SC3 (PEZY Super Computer 3) is fourth generation many-core microprocessor planned by PEZY. The SC3 is planned to have at least 8192 cores, twice as many cores as its predecessor.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Memory controller
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Integrated Memory Controller
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Integrated Memory Controller
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Facts about "PEZY-SC3 - PEZY"
| has ecc memory support | true + and false + |
| max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + and 11,448.32 GiB/s (11,723,079.68 MiB/s, 12,292.54 GB/s, 12,292,539.999 MB/s, 11.18 TiB/s, 12.293 TB/s) + |
| max memory channels | 4 + and 8 + |
| supported memory type | DDR4-3600 + |