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Difference between revisions of "pezy/pezy-scx/pezy-sc2"
< pezy‎ | pezy-scx

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|power=200 W
 
|power=200 W
 
|v core=0.8 V
 
|v core=0.8 V
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|electrical=Yes
 
 
}}
 
}}
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'''PEZY-SC2''' ('''PEZY Super Computer 2''') is third generation [[many-core microprocessor]] developed by [[PEZY]] set to be released in late 2016 or early 2017. The SC2 is planned to have 4096 cores, 4 times as many cores as its predecessor. Unlike the {{pezy|PEZY-SC}} which had 2 {{armh|ARM926}}, the SC2 will be replaced by 12 {{mips|MIPS64}} cores.
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'''PEZY-SC2''' ('''PEZY Super Computer 2''') is third generation [[many-core microprocessor]] developed by [[PEZY]] released in early 2017. The SC2 incorporates 2,048 cores, twice as many cores as its predecessor. Unlike the {{pezy|PEZY-SC}} which had 2 {{armh|ARM926}}, the SC2 will be replaced by 12 {{mips|MIPS64}} cores.
  
 
PEZY-SC2 is planned to operate at 1 GHz and consume around 100 W while delivering performance in the order of 16.4 TFLOPS (single-precision) and 8.2 TFLOPS (double precision). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's [[16 nm process]].
 
PEZY-SC2 is planned to operate at 1 GHz and consume around 100 W while delivering performance in the order of 16.4 TFLOPS (single-precision) and 8.2 TFLOPS (double precision). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's [[16 nm process]].
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{{unknown features}}
 
{{unknown features}}
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== Memory controller ==
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{{memory controller
 +
|type=DDR4-2666
 +
|ecc=Yes
 +
|controllers=8
 +
|channels=8
 +
|max bandwidth=158.95 GiB/s
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|bandwidth schan=19.89 GiB/s
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|bandwidth dchan=39.72 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
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|bandwidth ochan=158.95 GiB/s
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|bandwidth hchan=119.21 GiB/s
 +
}}
 +
 +
{{memory controller
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|wide-io clock=2,000 MHz
 +
|wide-io width=1,024 bit
 +
|channels=4
 +
|max bandwidth=1.863 TiB/s
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}}

Revision as of 04:56, 23 June 2017

Template:mpu PEZY-SC2 (PEZY Super Computer 2) is third generation many-core microprocessor developed by PEZY released in early 2017. The SC2 incorporates 2,048 cores, twice as many cores as its predecessor. Unlike the PEZY-SC which had 2 ARM926, the SC2 will be replaced by 12 MIPS64 cores.

PEZY-SC2 is planned to operate at 1 GHz and consume around 100 W while delivering performance in the order of 16.4 TFLOPS (single-precision) and 8.2 TFLOPS (double precision). The PEZY-SC2 is designed using over 2.4 billion gates and will be manufactured on TSMC's 16 nm process.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Controllers8
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
MemoryWide I/O
Rate2,000 MHz
Width1,024 bit
Channels4
Max Bandwidth1.863 TiB/s
1,907.712 GiB/s
1,953,497.088 MiB/s
2,048.39 GB/s
2,048,390.163 MB/s
2.048 TB/s
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Facts about "PEZY-SC2 - PEZY"
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has ecc memory supporttrue + and false +
max memory bandwidth158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + and 1,907.712 GiB/s (1,953,497.088 MiB/s, 2,048.39 GB/s, 2,048,390.163 MB/s, 1.863 TiB/s, 2.048 TB/s) +
max memory channels8 + and 4 +
supported memory typeDDR4-2666 +