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Difference between revisions of "cavium/octeon plus/cn5745-600bg1217-sp"
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'''CN5745-600 SP''' is a {{arch|64}} [[deca-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates ten {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration. | '''CN5745-600 SP''' is a {{arch|64}} [[deca-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates ten {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration. | ||
Revision as of 23:26, 22 June 2017
Template:mpu CN5745-600 SP is a 64-bit deca-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates ten cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
- 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
- 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
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Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram
Datasheet
Facts about "CN5745-600 SP - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5745-600 SP - Cavium#io + |
| has ecc memory support | true + |
| has hardware accelerators for data compression | true + |
| has hardware accelerators for data decompression | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| has hardware raid 5 support | true + |
| has hardware raid 6 support | true + |
| l1$ size | 480 KiB (491,520 B, 0.469 MiB) + |
| l1d$ size | 160 KiB (163,840 B, 0.156 MiB) + |
| l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 8 + |
| supported memory type | DDR2-800 + |