Semiconductor & Computer Engineering
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Difference between revisions of "amd/epyc/7251"
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|frequency=2,100 MHz | |frequency=2,100 MHz | ||
|turbo frequency1=2,900 MHz | |turbo frequency1=2,900 MHz | ||
| + | |turbo frequency2=2,900 MHz | ||
| + | |turbo frequency3=2,900 MHz | ||
| + | |turbo frequency4=2,900 MHz | ||
| + | |turbo frequency5=2,900 MHz | ||
| + | |turbo frequency6=2,900 MHz | ||
| + | |turbo frequency7=2,900 MHz | ||
| + | |turbo frequency8=2,900 MHz | ||
|bus links=4 | |bus links=4 | ||
|bus rate=8 GT/s | |bus rate=8 GT/s | ||
Revision as of 21:02, 20 June 2017
Template:mpu EPYC 7251 is a dual-socket 64-bit octa-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7251 has a base frequency of 2.1 GHz with a turbo frequency of 2.9 GHz for a single active core. This chip has a TDP of 120 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Contents
Cache
- Main article: Zen § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
The EPYC 7351P has 128 Gen 3 PCIe lanes.
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Expansion Options
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "EPYC 7251 - AMD"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 7251 - AMD#io + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has amd amd-v technology | true + |
| has amd amd-vi technology | true + |
| has amd sensemi technology | true + |
| has ecc memory support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
| has simultaneous multithreading | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
| max memory bandwidth | 158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + |
| max memory channels | 8 + |
| max pcie lanes | 128 + |
| supported memory type | DDR4-2666 + |