From WikiChip
Difference between revisions of "amd/epyc/7401"
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|ecc=Yes | |ecc=Yes | ||
|max mem=2 TiB | |max mem=2 TiB | ||
− | |controllers= | + | |controllers=4 |
|channels=8 | |channels=8 | ||
|max bandwidth=158.95 GiB/s | |max bandwidth=158.95 GiB/s | ||
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|bandwidth dchan=39.72 GiB/s | |bandwidth dchan=39.72 GiB/s | ||
|bandwidth qchan=79.47 GiB/s | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth ochan=158.95 GiB/s | ||
|bandwidth hchan=119.21 GiB/s | |bandwidth hchan=119.21 GiB/s | ||
− | |||
}} | }} | ||
Revision as of 21:14, 20 June 2017
Template:mpu EPYC 7401 is a dual-socket 64-bit 24-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7401 has a base frequency of 2 GHz with a turbo frequency of 3.0 GHz for a single active core. This chip has a TDP of 170W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket. The TDP is slightly lower at 155 W if DDR4-2400 is used instead.
Contents
Cache
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
The EPYC 7401P has 128 Gen 3 PCIe lanes.
Expansion Options
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Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "EPYC 7401 - AMD"