From WikiChip
Difference between revisions of "amd/epyc/7301"
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|ecc=Yes | |ecc=Yes | ||
|max mem=2 TiB | |max mem=2 TiB | ||
− | |controllers= | + | |controllers=4 |
|channels=8 | |channels=8 | ||
|max bandwidth=158.95 GiB/s | |max bandwidth=158.95 GiB/s | ||
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|bandwidth dchan=39.72 GiB/s | |bandwidth dchan=39.72 GiB/s | ||
|bandwidth qchan=79.47 GiB/s | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth ochan=158.95 GiB/s | ||
|bandwidth hchan=119.21 GiB/s | |bandwidth hchan=119.21 GiB/s | ||
− | |||
}} | }} | ||
Revision as of 20:13, 20 June 2017
Template:mpu EPYC 7301 is a dual-socket 64-bit 16-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7301 has a base frequency of 2.2 GHz with a turbo frequency of 2.7 GHz for a single active core. This chip has a TDP of 170 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket. The TDP is slightly lower at 155 W if DDR4-2400 is used instead.
Contents
Cache
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
The EPYC 7351P has 128 Gen 3 PCIe lanes.
Expansion Options
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Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "EPYC 7301 - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 7301 - AMD#io + |
base frequency | 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
clock multiplier | 22 + |
core count | 16 + |
core family | 23 + |
core model | 1 + |
core name | Naples + |
core stepping | B2 + |
designer | AMD + |
die area | 213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) + |
die count | 4 + |
family | EPYC + |
first announced | June 20, 2017 + |
first launched | June 20, 2017 + |
full page name | amd/epyc/7301 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd secure encrypted virtualization technology | true + |
has amd secure memory encryption technology | true + |
has amd sensemi technology | true + |
has amd transparent secure memory encryption technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
has locked clock multiplier | false + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
ldate | June 20, 2017 + |
manufacturer | GlobalFoundries + |
market segment | Server + |
max case temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
max cpu count | 2 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + |
max memory channels | 8 + |
max pcie lanes | 128 + |
microarchitecture | Zen + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 7301 + |
name | EPYC 7301 + |
package | FCLGA-4094 + and SP3 + |
part number | PS7301BEVGPAF + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 825.00 (€ 742.50, £ 668.25, ¥ 85,247.25) + |
series | 7000 + |
smp max ways | 2 + |
socket | SP3 + and LGA-4094 + |
supported memory type | DDR4-2666 + and DDR4-2400 + |
tdp | 155 W (155,000 mW, 0.208 hp, 0.155 kW) + and 170 W (170,000 mW, 0.228 hp, 0.17 kW) + |
technology | CMOS + |
thread count | 32 + |
transistor count | 19,200,000,000 + |
turbo frequency (10 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (11 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (12 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (13 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (14 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (15 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (16 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (1 core) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (2 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (3 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (4 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (5 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (6 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (7 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (8 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (9 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |