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Difference between revisions of "amd/epyc/7401p"
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{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{cache size
 
{{cache size
−
|l1 cache=1.5 MiB
+
|l1 cache=2.25 MiB
−
|l1i cache=1 MiB
+
|l1i cache=1.5 MiB
−
|l1i break=16x64 KiB
+
|l1i break=24x64 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
−
|l1d cache=512 KiB
+
|l1d cache=768 KiB
 
|l1d break=16x32 KiB
 
|l1d break=16x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d policy=write-back
 
|l1d policy=write-back
−
|l2 cache=8 MiB
+
|l2 cache=12 MiB
−
|l2 break=16x512 KiB
+
|l2 break=24x512 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back

Revision as of 18:20, 20 June 2017

Template:mpu EPYC 7401P is a 64-bit 24-core x86 enterprise server microprocessor introduced by AMD in mid-2017. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7401P has a base frequency of 2 GHz with a turbo frequency of 3.0 GHz for a single active core. This chip has a TDP of 170W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory. The TDP is slightly lower at 155W if DDR4-2400 is used instead.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2.25 MiB
2,304 KiB
2,359,296 B
L1I$1.5 MiB
1,536 KiB
1,572,864 B
24x64 KiB4-way set associative 
L1D$768 KiB
786,432 B
0.75 MiB
16x32 KiB8-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  24x512 KiB8-way set associativewrite-back
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  8x8 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem2 TiB
Controllers1
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SenseMISenseMI Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc/7401p&oldid=45269"
Facts about "EPYC 7401P - AMD"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC 7401P - AMD#io +
base frequency2,000 MHz (2 GHz, 2,000,000 kHz) +
clock multiplier20 +
core count24 +
core family23 +
core model1 +
core nameNaples +
core steppingB2 +
designerAMD +
die area213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count4 +
familyEPYC +
first announcedJune 20, 2017 +
first launchedJune 20, 2017 +
full page nameamd/epyc/7401p +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd secure encrypted virtualization technologytrue +
has amd secure memory encryption technologytrue +
has amd sensemi technologytrue +
has amd transparent secure memory encryption technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multiplierfalse +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size2,304 KiB (2,359,296 B, 2.25 MiB) +
l1d$ description8-way set associative +
l1d$ size768 KiB (786,432 B, 0.75 MiB) +
l1i$ description4-way set associative +
l1i$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description8-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description16-way set associative +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldateJune 20, 2017 +
manufacturerGlobalFoundries +
market segmentServer +
max case temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
max cpu count1 +
max memory2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels8 +
max pcie lanes128 +
microarchitectureZen +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number7401P +
nameEPYC 7401P +
packageFCLGA-4094 + and SP3 +
part numberPS740PBEVHCAF +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 1,075.00 (€ 967.50, £ 870.75, ¥ 111,079.75) +
series7000 +
smp max ways1 +
socketSP3 + and LGA-4094 +
supported memory typeDDR4-2666 + and DDR4-2400 +
tdp155 W (155,000 mW, 0.208 hp, 0.155 kW) + and 170 W (170,000 mW, 0.228 hp, 0.17 kW) +
technologyCMOS +
thread count48 +
transistor count19,200,000,000 +
turbo frequency (10 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (11 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (12 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (13 cores)2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (14 cores)2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (15 cores)2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (16 cores)2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (17 cores)2,800 MHz +
turbo frequency (18 cores)2,800 MHz +
turbo frequency (19 cores)2,800 MHz +
turbo frequency (1 core)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (20 cores)2,800 MHz +
turbo frequency (21 cores)2,800 MHz +
turbo frequency (22 cores)2,800 MHz +
turbo frequency (23 cores)2,800 MHz +
turbo frequency (24 cores)2,800 MHz +
turbo frequency (2 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (3 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (4 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (5 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (6 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (7 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (8 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (9 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +