From WikiChip
					
    Difference between revisions of "intel/xeon e3/e3-1205 v6"    
                	
														 (+stepping)  | 
				|||
| Line 1: | Line 1: | ||
{{intel title|Xeon E3-1205 v6}}  | {{intel title|Xeon E3-1205 v6}}  | ||
{{mpu  | {{mpu  | ||
| − | |||
| name                = Xeon E3-1205 v6  | | name                = Xeon E3-1205 v6  | ||
| no image            = Yes  | | no image            = Yes  | ||
| Line 14: | Line 13: | ||
| s-spec              = SR32D  | | s-spec              = SR32D  | ||
| market              = Workstation  | | market              = Workstation  | ||
| − | | first announced     =    | + | | market 2            = Server  | 
| − | | first launched      = 2017  | + | | first announced     = March 28, 2017  | 
| + | | first launched      = March 28, 2017  | ||
| last order          =    | | last order          =    | ||
| last shipment       =    | | last shipment       =    | ||
| − | | release price       =    | + | | release price       = $193  | 
| family              = Xeon E3  | | family              = Xeon E3  | ||
| Line 24: | Line 24: | ||
| locked              = Yes  | | locked              = Yes  | ||
| frequency           = 3,000 MHz  | | frequency           = 3,000 MHz  | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| bus type            = DMI 3.0  | | bus type            = DMI 3.0  | ||
| bus speed           =    | | bus speed           =    | ||
| Line 63: | Line 58: | ||
| v core max          = 1.52 V  | | v core max          = 1.52 V  | ||
| sdp                 =    | | sdp                 =    | ||
| − | | tdp                 =   | + | | tdp                 = 65 W  | 
| tdp typical         =    | | tdp typical         =    | ||
| ctdp down           =    | | ctdp down           =    | ||
| Line 80: | Line 75: | ||
| package module 1    = {{packages/intel/lga-1151}}  | | package module 1    = {{packages/intel/lga-1151}}  | ||
}}  | }}  | ||
| − | '''Xeon E3-1205 v6''' is a {{arch|64}} [[quad-core]] [[x86]] workstation/entry server microprocessor set to be introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The E3-1205 v6 operates at 3 GHz with a TDP of   | + | '''Xeon E3-1205 v6''' is a {{arch|64}} [[quad-core]] [[x86]] workstation/entry server microprocessor set to be introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The E3-1205 v6 operates at 3 GHz with a TDP of 65 W with no {{intel|Turbo Boost}}. The processor supports up to 64 GiB of dual-channel DDR4-2400 ECC memory and incorporates Intel's {{intel|HD Graphics P630}} [[IGP]] operating at 350 MHz with a burst frequency of 1 GHz.  | 
| − | |||
| − | |||
| − | |||
== Cache ==  | == Cache ==  | ||
| Line 131: | Line 123: | ||
{{integrated graphics  | {{integrated graphics  | ||
| gpu                 = HD Graphics P630  | | gpu                 = HD Graphics P630  | ||
| − | | device id           =   | + | | device id           = 0x191D  | 
| designer            = Intel  | | designer            = Intel  | ||
| execution units     = 24  | | execution units     = 24  | ||
| Line 137: | Line 129: | ||
| max memory          = 1.7 GiB  | | max memory          = 1.7 GiB  | ||
| frequency           = 350 MHz  | | frequency           = 350 MHz  | ||
| − | | max frequency       = 1,  | + | | max frequency       = 1,000 MHz  | 
| output crt          =    | | output crt          =    | ||
| Line 210: | Line 202: | ||
|f16c=Yes  | |f16c=Yes  | ||
|tbt1=No  | |tbt1=No  | ||
| − | |tbt2=  | + | |tbt2=No  | 
|tbmt3=No  | |tbmt3=No  | ||
|bpt=No  | |bpt=No  | ||
Revision as of 17:30, 24 April 2017
Template:mpu Xeon E3-1205 v6 is a 64-bit quad-core x86 workstation/entry server microprocessor set to be introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The E3-1205 v6 operates at 3 GHz with a TDP of 65 W with no Turbo Boost. The processor supports up to 64 GiB of dual-channel DDR4-2400 ECC memory and incorporates Intel's HD Graphics P630 IGP operating at 350 MHz with a burst frequency of 1 GHz.
Cache
- Main article: Kaby Lake § Cache
 
| 
 Cache Organization  
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.  | 
|||||||||||||||||||||||||||||||||||||
  | 
|||||||||||||||||||||||||||||||||||||
Memory controller
| 
 Integrated Memory Controller 
 | 
||||||||||||||
  | 
||||||||||||||
Expansions
| 
 Expansion Options 
 | 
||||||||
  | 
||||||||
Graphics
| 
 Integrated Graphics Information 
 | 
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
  | 
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| [Edit] Kaby Lake (Gen9.5) Hardware Accelerated Video Capabilities | |||||||
|---|---|---|---|---|---|---|---|
| Codec | Encode | Decode | |||||
| Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
| MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
| MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, MVC, Stereo | 5.1 | 2160p (4K) | |
| JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
| HEVC (H.265) | Main, Main 10 | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
| VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | 3840x3840 | |||
| VP8 | Unified | Unified | N/A | 0 | Unified | 1080p | |
| VP9 | 0 | 2160p (4K) | 0, 2 | Unified | 2160p (4K) | ||
Features
[Edit/Modify Supported Features]
Facts about "Xeon E3-1205 v6  - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.  | Xeon E3-1205 v6 - Intel#io + | 
| device id | 0x191D + | 
| has advanced vector extensions | true + | 
| has advanced vector extensions 2 | true + | 
| has ecc memory support | true + | 
| has extended page tables support | true + | 
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard + and Smart Response Technology + | 
| has intel enhanced speedstep technology | true + | 
| has intel secure key technology | true + | 
| has intel smart response technology support | true + | 
| has intel speed shift technology | true + | 
| has intel supervisor mode execution protection | true + | 
| has intel trusted execution technology | true + | 
| has intel vpro technology | true + | 
| has intel vt-d technology | true + | 
| has intel vt-x technology | true + | 
| has second level address translation support | true + | 
| has simultaneous multithreading | true + | 
| has transactional synchronization extensions | true + | 
| has x86 advanced encryption standard instruction set extension | true + | 
| integrated gpu | HD Graphics P630 + | 
| integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + | 
| integrated gpu designer | Intel + | 
| integrated gpu execution units | 24 + | 
| integrated gpu max frequency | 1,000 MHz (1 GHz, 1,000,000 KHz) + | 
| integrated gpu max memory | 1,740.8 MiB (1,782,579.2 KiB, 1,825,361,100.8 B, 1.7 GiB) + | 
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l2$ description | 4-way set associative + | 
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + | 
| l3$ description | 16-way set associative + | 
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + | 
| max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + | 
| max memory channels | 2 + | 
| max pcie lanes | 16 + | 
| supported memory type | DDR3L-1866 + and DDR4-2400 + | 
| x86/has memory protection extensions | true + | 
| x86/has software guard extensions | true + |