Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "Template:nodes comp"
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-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 volt|}}} }}<!-- | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 volt|}}} }}<!-- | ||
-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 volt|}}} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 volt|}}} }} | ||
| + | |- style="text-align: center;" | ||
| + | | colspan="2" | {{{process 1 layers|}}}<!-- | ||
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 layers|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 layers|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 layers|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 layers|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 layers|}}} }} | ||
|- | |- | ||
! Value !! {{{process 1 delta from|}}}<!-- | ! Value !! {{{process 1 delta from|}}}<!-- | ||
Revision as of 19:58, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Metal Layers | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | |
|---|---|