Semiconductor & Computer Engineering
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Difference between revisions of "Template:finfet nodes comp"
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-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 fin pitch Δ|}}} || {{{process 6 fin pitch Δ|}}} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 fin pitch Δ|}}} || {{{process 6 fin pitch Δ|}}} }} | ||
|- | |- | ||
| − | | {{{process 1 fin width|}}} || {{{process 1 fin width Δ|}}} || {{{process 2 fin width|}}} || {{{process 2 fin width Δ|}}} || {{{process 3 fin width|}}} || {{{process 3 fin width Δ|}}} | + | | {{{process 1 fin width|}}} || {{{process 1 fin width Δ|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 fin width Δ|}}} || {{{process 2 fin width Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 fin width Δ|}}} || {{{process 3 fin width Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 fin width Δ|}}} || {{{process 4 fin width Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 fin width Δ|}}} || {{{process 5 fin width Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 fin width Δ|}}} || {{{process 6 fin width Δ|}}} }} | ||
|- | |- | ||
| − | | {{{process 1 fin height|}}} || {{{process 1 fin height Δ|}}} || {{{process 2 fin height|}}} || {{{process 2 fin height Δ|}}} || {{{process 3 fin height|}}} || {{{process 3 fin height Δ|}}} | + | | {{{process 1 fin height|}}} || {{{process 1 fin height Δ|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 fin height Δ|}}} || {{{process 2 fin height Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 fin height Δ|}}} || {{{process 3 fin height Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 fin height Δ|}}} || {{{process 4 fin height Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 fin height Δ|}}} || {{{process 5 fin height Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 fin height Δ|}}} || {{{process 6 fin height Δ|}}} }} | ||
|- | |- | ||
| − | | {{{process 1 gate len|}}} || {{{process 1 gate len Δ|}}} || {{{process 2 gate len|}}} || {{{process 2 gate len Δ|}}} || {{{process 3 gate len|}}} || {{{process 3 gate len Δ|}}} | + | | {{{process 1 gate len|}}} || {{{process 1 gate len Δ|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 gate len Δ|}}} || {{{process 2 gate len Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 gate len Δ|}}} || {{{process 3 gate len Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 gate len Δ|}}} || {{{process 4 gate len Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 gate len Δ|}}} || {{{process 5 gate len Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 gate len Δ|}}} || {{{process 6 gate len Δ|}}} }} | ||
|- | |- | ||
| − | | {{{process 1 cpp|}}} || {{{process 1 cpp Δ|}}} || {{{process 2 cpp|}}} || {{{process 2 cpp Δ|}}} || {{{process 3 cpp|}}} || {{{process 3 cpp Δ|}}} | + | | {{{process 1 cpp|}}} || {{{process 1 cpp Δ|}}}<!-- |
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 cpp Δ|}}} || {{{process 2 cpp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 cpp Δ|}}} || {{{process 3 cpp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 cpp Δ|}}} || {{{process 4 cpp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 cpp Δ|}}} || {{{process 5 cpp Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 cpp Δ|}}} || {{{process 6 cpp Δ|}}} }} | ||
|- | |- | ||
| {{{process 1 mmp|}}} || {{{process 1 mmp Δ|}}} || {{{process 2 mmp|}}} || {{{process 2 mmp Δ|}}} || {{{process 3 mmp|}}} || {{{process 3 mmp Δ|}}} | | {{{process 1 mmp|}}} || {{{process 1 mmp Δ|}}} || {{{process 2 mmp|}}} || {{{process 2 mmp Δ|}}} || {{{process 3 mmp|}}} || {{{process 3 mmp Δ|}}} | ||
Revision as of 03:34, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | |||||
|---|---|---|---|---|---|