Semiconductor & Computer Engineering
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Difference between revisions of "Template:finfet nodes comp"
| Line 72: | Line 72: | ||
-->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 volt|}}} }}<!-- | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 volt|}}} }}<!-- | ||
-->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 volt|}}} }} | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 volt|}}} }} | ||
| + | |- | ||
| + | ! colspan="2" | Value !! {{{process 1 delta from|}}}<!-- | ||
| + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} Value {{!}}{{!}} colspan="2" {{!}} {{{process 2 delta from|}}} }}<!-- | ||
| + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} Value {{!}}{{!}} colspan="2" {{!}} {{{process 3 delta from|}}} }}<!-- | ||
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} Value {{!}}{{!}} colspan="2" {{!}} {{{process 4 delta from|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} Value {{!}}{{!}} colspan="2" {{!}} {{{process 5 delta from|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} Value {{!}}{{!}} colspan="2" {{!}} {{{process 6 delta from|}}} }} | ||
|- | |- | ||
| − | + | | {{process 1 fin pitch|}}} || {{process 1 fin pitch Δ|}}}<!-- | |
| − | |- | + | -->{{#if: {{{process 2 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 2 fin pitch Δ|}}} || {{process 2 fin pitch Δ|}}} }}<!-- |
| − | | {{{process | + | -->{{#if: {{{process 3 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 3 fin pitch Δ|}}} || {{process 3 fin pitch Δ|}}} }}<!-- |
| + | -->{{#if: {{{process 4 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 4 fin pitch Δ|}}} || {{process 4 fin pitch Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 5 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 5 fin pitch Δ|}}} || {{process 5 fin pitch Δ|}}} }}<!-- | ||
| + | -->{{#if: {{{process 6 fab|}}}| {{!}}{{!}} colspan="2" {{!}} {{{process 6 fin pitch Δ|}}} || {{process 6 fin pitch Δ|}}} }} | ||
|- | |- | ||
| {{{process 1 fin width|}}} || {{{process 1 fin width Δ|}}} || {{{process 2 fin width|}}} || {{{process 2 fin width Δ|}}} || {{{process 3 fin width|}}} || {{{process 3 fin width Δ|}}} | | {{{process 1 fin width|}}} || {{{process 1 fin width Δ|}}} || {{{process 2 fin width|}}} || {{{process 2 fin width Δ|}}} || {{{process 3 fin width|}}} || {{{process 3 fin width Δ|}}} | ||
Revision as of 03:18, 5 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |