Semiconductor & Computer Engineering
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Difference between revisions of "Template:finfet nodes comp"
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| − | + | ! colspan="2" | {{{process 1 fab|}}} || colspan="2" | {{{process 2 fab|}}} || colspan="2" | {{{process 3 fab|}}} | |
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| colspan="2" | {{{process 1 name|}}} || colspan="2" | {{{process 2 name|}}} || colspan="2" | {{{process 3 name|}}} | | colspan="2" | {{{process 1 name|}}} || colspan="2" | {{{process 2 name|}}} || colspan="2" | {{{process 3 name|}}} | ||
Revision as of 23:56, 4 April 2017
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Fin | Pitch |
| Width | |
| Height | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |
| Value | Value | Value | |||
|---|---|---|---|---|---|