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Difference between revisions of "Template:finfet nodes comp"
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{| class="wikitable" style="margin:0; {{{style|}}}" | {| class="wikitable" style="margin:0; {{{style|}}}" | ||
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | {{{process 1 fab}}} || colspan="2" | {{{process 2 fab}}} || colspan="2" | {{{process 3 fab}}} | + | | colspan="2" | {{{process 1 fab|}}} || colspan="2" | {{{process 2 fab|}}} || colspan="2" | {{{process 3 fab|}}} |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | {{{process 1 name}}} || colspan="2" | {{{process 2 name}}} || colspan="2" | {{{process 3 name}}} | + | | colspan="2" | {{{process 1 name|}}} || colspan="2" | {{{process 2 name|}}} || colspan="2" | {{{process 3 name|}}} |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | {{{process 1 date}}} || colspan="2" | {{{process 2 date}}} || colspan="2" | {{{process 3 date}}} | + | | colspan="2" | {{{process 1 date|}}} || colspan="2" | {{{process 2 date|}}} || colspan="2" | {{{process 3 date|}}} |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | {{{process 1 wafer type}}} || colspan="2" | {{{process 2 wafer type}}} || colspan="2" | {{{process 3 wafer type}}} | + | | colspan="2" | {{{process 1 wafer type|}}} || colspan="2" | {{{process 2 wafer type|}}} || colspan="2" | {{{process 3 wafer type|}}} |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | {{{process 1 wafer size}}} || colspan="2" | {{{process 2 wafer size}}} || colspan="2" | {{{process 3 wafer size}}} | + | | colspan="2" | {{{process 1 wafer size|}}} || colspan="2" | {{{process 2 wafer size|}}} || colspan="2" | {{{process 3 wafer size|}}} |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | {{{process 1 wafer type}}} || colspan="2" | {{{process 2 wafer type}}} || colspan="2" | {{{process 3 wafer type}}} | + | | colspan="2" | {{{process 1 wafer type|}}} || colspan="2" | {{{process 2 wafer type|}}} || colspan="2" | {{{process 3 wafer type|}}} |
|- style="text-align: center;" | |- style="text-align: center;" | ||
− | | colspan="2" | {{{process 1 volt}}} || colspan="2" | {{{process 2 volt}}} || colspan="2" | {{{process 3 volt}}} | + | | colspan="2" | {{{process 1 volt|}}} || colspan="2" | {{{process 2 volt|}}} || colspan="2" | {{{process 3 volt|}}} |
|- | |- | ||
− | ! Value !! {{{process 1 delta from}}} !! Value !! {{{process 2 delta from}}} !! Value !! {{{process 3 delta from}}} | + | ! Value !! {{{process 1 delta from|}}} !! Value !! {{{process 2 delta from|}}} !! Value !! {{{process 3 delta from|}}} |
|- | |- | ||
− | | {{{process 1 fin pitch}}} || {{{process 1 fin pitch Δ}}} || {{{process 2 fin pitch}}} || {{{process 2 fin pitch Δ}}} || {{{process 3 fin pitch}}} || {{{process 3 fin pitch Δ}}} | + | | {{{process 1 fin pitch|}}} || {{{process 1 fin pitch Δ|}}} || {{{process 2 fin pitch|}}} || {{{process 2 fin pitch Δ|}}} || {{{process 3 fin pitch|}}} || {{{process 3 fin pitch Δ|}}} |
|- | |- | ||
− | | {{{process 1 fin width}}} || {{{process 1 fin width Δ}}} || {{{process 2 fin width}}} || {{{process 2 fin width Δ}}} || {{{process 3 fin width}}} || {{{process 3 fin width Δ}}} | + | | {{{process 1 fin width|}}} || {{{process 1 fin width Δ|}}} || {{{process 2 fin width|}}} || {{{process 2 fin width Δ|}}} || {{{process 3 fin width|}}} || {{{process 3 fin width Δ|}}} |
|- | |- | ||
− | | {{{process 1 fin height}}} || {{{process 1 fin height Δ}}} || {{{process 2 fin height}}} || {{{process 2 fin height Δ}}} || {{{process 3 fin height}}} || {{{process 3 fin height Δ}}} | + | | {{{process 1 fin height|}}} || {{{process 1 fin height Δ|}}} || {{{process 2 fin height|}}} || {{{process 2 fin height Δ|}}} || {{{process 3 fin height|}}} || {{{process 3 fin height Δ|}}} |
|- | |- | ||
− | | {{{process 1 gate len}}} || {{{process 1 gate len Δ}}} || {{{process 2 gate len}}} || {{{process 2 gate len Δ}}} || {{{process 3 gate len}}} || {{{process 3 gate len Δ}}} | + | | {{{process 1 gate len|}}} || {{{process 1 gate len Δ|}}} || {{{process 2 gate len|}}} || {{{process 2 gate len Δ|}}} || {{{process 3 gate len|}}} || {{{process 3 gate len Δ|}}} |
|- | |- | ||
− | | {{{process 1 cpp}}} || {{{process 1 cpp Δ}}} || {{{process 2 cpp}}} || {{{process 2 cpp Δ}}} || {{{process 3 cpp}}} || {{{process 3 cpp Δ}}} | + | | {{{process 1 cpp|}}} || {{{process 1 cpp Δ|}}} || {{{process 2 cpp|}}} || {{{process 2 cpp Δ|}}} || {{{process 3 cpp|}}} || {{{process 3 cpp Δ|}}} |
|- | |- | ||
− | | {{{process 1 mmp}}} || {{{process 1 mmp Δ}}} || {{{process 2 mmp}}} || {{{process 2 mmp Δ}}} || {{{process 3 mmp}}} || {{{process 3 mmp Δ}}} | + | | {{{process 1 mmp|}}} || {{{process 1 mmp Δ|}}} || {{{process 2 mmp|}}} || {{{process 2 mmp Δ|}}} || {{{process 3 mmp|}}} || {{{process 3 mmp Δ|}}} |
|- | |- | ||
− | | {{{process 1 sram hp}}} || {{{process 1 sram hp Δ}}} || {{{process 2 sram hp}}} || {{{process 2 sram hp Δ}}} || {{{process 3 sram hp}}} || {{{process 3 sram hp Δ}}} | + | | {{{process 1 sram hp|}}} || {{{process 1 sram hp Δ|}}} || {{{process 2 sram hp|}}} || {{{process 2 sram hp Δ|}}} || {{{process 3 sram hp|}}} || {{{process 3 sram hp Δ|}}} |
|- | |- | ||
− | | {{{process 1 sram hd}}} || {{{process 1 sram hd Δ}}} || {{{process 2 sram hd}}} || {{{process 2 sram hd Δ}}} || {{{process 3 sram hd}}} || {{{process 3 sram hd Δ}}} | + | | {{{process 1 sram hd|}}} || {{{process 1 sram hd Δ|}}} || {{{process 2 sram hd|}}} || {{{process 2 sram hd Δ|}}} || {{{process 3 sram hd|}}} || {{{process 3 sram hd Δ|}}} |
|- | |- | ||
− | | {{{process 1 sram lv}}} || {{{process 1 sram lv Δ}}} || {{{process 2 sram lv}}} || {{{process 2 sram lv Δ}}} || {{{process 3 sram lv}}} || {{{process 3 sram lv Δ}}} | + | | {{{process 1 sram lv|}}} || {{{process 1 sram lv Δ|}}} || {{{process 2 sram lv|}}} || {{{process 2 sram lv Δ|}}} || {{{process 3 sram lv|}}} || {{{process 3 sram lv Δ|}}} |
|- | |- | ||
− | | {{{process 1 dram}}} || {{{process 1 dram Δ}}} || {{{process 2 dram}}} || {{{process 2 dram Δ}}} || {{{process 3 dram}}} || {{{process 3 dram Δ}}} | + | | {{{process 1 dram|}}} || {{{process 1 dram Δ|}}} || {{{process 2 dram|}}} || {{{process 2 dram Δ|}}} || {{{process 3 dram|}}} || {{{process 3 dram Δ|}}} |
|} | |} |
Revision as of 22:54, 4 April 2017
Process Name | |
---|---|
1st Production | |
Lithography | Lithography |
Immersion | |
Exposure | |
Wafer | Type |
Size | |
Transistor | Type |
Voltage | |
Fin | Pitch |
Width | |
Height | |
Gate Length (Lg) | |
Contacted Gate Pitch (CPP) | |
Minimum Metal Pitch (MMP) | |
SRAM bitcell | High-Perf (HP) |
High-Density (HD) | |
Low-Voltage (LV) | |
DRAM bitcell | eDRAM |
Value | Value | Value | |||
---|---|---|---|---|---|