Semiconductor & Computer Engineering
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Difference between revisions of "baikal/baikal-m"
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| − | '''Baikal-M''' is an [[octa-core]] {{arch|64}} [[ARM]] system on a chip set to be introduced by [[Baikal Electronics]] in late [[2017]]. | + | '''Baikal-M''' is an [[octa-core]] {{arch|64}} [[ARM]] system on a chip set to be introduced by [[Baikal Electronics]] in late [[2017]]. This chip, which is fabricated on [[TSMC]]'s [[28 nm process]], operates at 2 GHz and integrates an [[ARM Holdings|ARM]] {{armh|Mali-T628}} MP8 [[IGP]]. |
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|max bandwidth=11.92 GiB/s | |max bandwidth=11.92 GiB/s | ||
|bandwidth schan=11.92 GiB/s | |bandwidth schan=11.92 GiB/s | ||
| + | }} | ||
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| + | == Graphics == | ||
| + | {{integrated graphics | ||
| + | | gpu = Mali-T628 | ||
| + | | device id = | ||
| + | | designer = ARM Holdings | ||
| + | | execution units = 8 | ||
| + | | max displays = | ||
| + | | max memory = | ||
| + | | frequency = ? MHz | ||
| + | |||
| + | | output dsi = Yes | ||
| + | |||
| + | | max res dsi = ? | ||
| + | |||
| + | | direct3d ver = 11 | ||
| + | | opencl ver = 1.1 | ||
| + | | opengl ver = 3.2 | ||
| + | | opengl es ver = 3.1 | ||
| + | | openvg ver = 1.1 | ||
}} | }} | ||
Revision as of 20:30, 21 March 2017
Template:mpu Baikal-M is an octa-core 64-bit ARM system on a chip set to be introduced by Baikal Electronics in late 2017. This chip, which is fabricated on TSMC's 28 nm process, operates at 2 GHz and integrates an ARM Mali-T628 MP8 IGP.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Graphics
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Integrated Graphics Information
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Expansions
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Expansion Options
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Networking
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Networking
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Facts about "Baikal-M - Baikal Electronics"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Baikal-M - Baikal Electronics#io + |
| base frequency | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
| core count | 8 + |
| core name | Cortex-A57 + |
| designer | ARM Holdings + |
| first announced | January 28, 2016 + |
| first launched | 2017 + |
| full page name | baikal/baikal-m + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| integrated gpu | Mali-T628 + |
| integrated gpu base frequency | 850 MHz (0.85 GHz, 850,000 KHz) + |
| integrated gpu designer | ARM Holdings + |
| integrated gpu execution units | 8 + |
| isa | ARMv8 + |
| isa family | ARM + |
| l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| ldate | 3000 + |
| manufacturer | TSMC + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| microarchitecture | Cortex-A57 + |
| model number | Baikal-M + |
| name | Baikal-M + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |
| series | Baikal + |
| supported memory type | DDR4-2400 + |
| thread count | 8 + |