From WikiChip
Difference between revisions of "baikal/baikal-m"
(Created page with "{{baikal title|Baikal-M}} {{mpu | future = Yes | name = Baikal-M | no image = Yes | image = | image size = | ca...") |
|||
Line 10: | Line 10: | ||
| designer = ARM Holdings | | designer = ARM Holdings | ||
| manufacturer = TSMC | | manufacturer = TSMC | ||
− | | model number = | + | | model number = Baikal-M |
| part number = | | part number = | ||
| part number 1 = | | part number 1 = |
Revision as of 19:47, 21 March 2017
Template:mpu Baikal-M is an octa-core 64-bit ARM system on a chip set to be introduced by Baikal Electronics in late 2017.
Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Expansions
Expansion Options
|
||||||||||||||||||||||||||||||||||||
|
Networking
Networking
|
||||||||||
|
Facts about "Baikal-M - Baikal Electronics"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Baikal-M - Baikal Electronics#io + |
has ecc memory support | true + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 1 + |
max pcie lanes | 4 + |
supported memory type | DDR4-1600 + |