Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "baikal/baikal-t1"
| Line 51: | Line 51: | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
}} | }} | ||
| − | '''Baikal-T1''' is a {{arch|32}} [[dual-core]] [[MIPS]] [[system on a chip]] introduced by [[Baikal Electronics]] in 2015 for the embedded market. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of [[Imagination Technologies]] high-performance P5600 cores and is manufactured on [[TSMC]]'s [[28 nm process]]. The Baikal-T1 supports up to 8 GiB of DDR3-1600. | + | '''Baikal-T1''' is a {{arch|32}} [[dual-core]] [[MIPS]] [[system on a chip]] introduced by [[Baikal Electronics]] in 2015 for the embedded market. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of [[Imagination Technologies|Imagination]] high-performance {{imgtec|P5600}} cores and is manufactured on [[TSMC]]'s [[28 nm process]]. The Baikal-T1 supports up to 8 GiB of DDR3-1600. |
The chip consumes less than 5W and can be used in fanless designs. | The chip consumes less than 5W and can be used in fanless designs. | ||
Revision as of 18:09, 21 March 2017
Template:mpu Baikal-T1 is a 32-bit dual-core MIPS system on a chip introduced by Baikal Electronics in 2015 for the embedded market. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of Imagination high-performance P5600 cores and is manufactured on TSMC's 28 nm process. The Baikal-T1 supports up to 8 GiB of DDR3-1600.
The chip consumes less than 5W and can be used in fanless designs.
Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
|||||||||||||||||||||||||
Memory controller
 |
Integrated Memory Controller
|
|||||||||||||
|
||||||||||||||
Expansions
 |
Expansion Options
|
|||||||||||||||||||||||||||||||||||
|
||||||||||||||||||||||||||||||||||||
Networking
 |
Networking
|
|||||||||
|
||||||||||
Block Diagram
Facts about "Baikal-T1 - Baikal Electronics"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Baikal-T1 - Baikal Electronics#io + |
| has ecc memory support | true + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 1 + |
| max pcie lanes | 4 + |
| supported memory type | DDR3-1600 + |