Semiconductor & Computer Engineering
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Difference between revisions of "baikal/baikal-t1"
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== Expansions == | == Expansions == | ||
| − | {{ | + | {{expansions |
| − | | pcie revision | + | |pcie revision=3.0 |
| − | | pcie lanes | + | |pcie lanes=4 |
| − | | pcie | + | |pcie config=x4 |
| − | | | + | |usb revision=2.0 |
| − | | | + | |usb rate=480 Mib/s |
| − | | | + | |usb extra=8-bit ULPI PHY |
| − | | | + | |uart=Yes |
| − | | | + | |uart ports=2 |
| − | | | + | |sata revision=3.1 |
| − | | | + | |sata ports=2 |
| − | | | + | |i2c=Yes |
| − | | | + | |i2c ports=2 |
| − | | | + | |gp io=32 bit |
| − | | | + | |jtag=Yes |
| − | | | + | |integrated lan=Yes |
}} | }} | ||
Revision as of 12:52, 21 March 2017
Template:mpu Baikal-T1 is a 32-bit dual-core MIPS system on a chip introduced by Baikal Electronics in 2015 for the embedded market. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of Imagination Technologies high-performance P5600 cores and is manufactured on TSMC's 28 nm process. The Baikal-T1 supports up to 8 GiB of DDR3-1600.
The chip consumes less than 5W and can be used in fanless designs.
Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
The Baikal-T1 has support for 1x10Gb and 2x1Gb Ethernet ports.
| Networking | |
| 1000Base-T | Yes |
| 10GBase-T | Yes |
Block Diagram
Facts about "Baikal-T1 - Baikal Electronics"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Baikal-T1 - Baikal Electronics#io + |
| base frequency | 1,200 MHz (1.2 GHz, 1,200,000 kHz) + |
| bus type | AXI + |
| core count | 2 + |
| core name | P5600 + |
| designer | Baikal Electronics + and Imagination Technologies + |
| first announced | June 1, 2015 + |
| first launched | February 2016 + |
| full page name | baikal/baikal-t1 + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| isa | MIPS32 + |
| isa family | MIPS + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| ldate | February 2016 + |
| main image |  + |
| manufacturer | TSMC + |
| market segment | Embedded + |
| max case temperature | 343.15 K (70 °C, 158 °F, 617.67 °R) + |
| max cpu count | 1 + |
| max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 1 + |
| max pcie lanes | 4 + |
| microarchitecture | P5600 + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| model number | Baikal-T1 + |
| name | Baikal-T1 + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |
| series | Baikal + |
| smp max ways | 1 + |
| supported memory type | DDR3-1600 + |
| tdp | 5 W (5,000 mW, 0.00671 hp, 0.005 kW) + |
| thread count | 2 + |
| word size | 32 bit (4 octets, 8 nibbles) + |
