From WikiChip
Difference between revisions of "cavium/octeon plus/cn5750-800bg1217-sp"
< cavium‎ | octeon plus

(Created page with "{{cavium title|CN5750-800 SP}} {{mpu | name = Cavium CN5750-800 SP | no image = | image = Octeon CN57xx.svg | image size = |...")
 
Line 83: Line 83:
 
| package 0 pins      = 1217
 
| package 0 pins      = 1217
 
| package 0 pitch    =  
 
| package 0 pitch    =  
| package 0 width    =  
+
| package 0 width    = 40 mm
| package 0 length    =  
+
| package 0 length    = 40 mm
 
| package 0 height    =  
 
| package 0 height    =  
 
| socket 0            = BGA-1217
 
| socket 0            = BGA-1217
 
| socket 0 type      = BGA
 
| socket 0 type      = BGA
 
}}
 
}}
 +
'''CN5750-800 SP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration.

Revision as of 01:50, 29 December 2016

Template:mpu CN5750-800 SP is a 64-bit dodeca-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 800 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.

Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5750-800 SP - Cavium#io +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
l1$ size576 KiB (589,824 B, 0.563 MiB) +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
supported memory typeDDR2-800 +