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Difference between revisions of "cavium/octeon plus/cn5745-600bg1217-sp"
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| package 0 pins = 1217 | | package 0 pins = 1217 | ||
| package 0 pitch = | | package 0 pitch = | ||
| − | | package 0 width = | + | | package 0 width = 40 mm |
| − | | package 0 length = | + | | package 0 length = 40 mm |
| package 0 height = | | package 0 height = | ||
| socket 0 = BGA-1217 | | socket 0 = BGA-1217 | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
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| + | '''CN5745-600 SP''' is a {{arch|64}} [[deca-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates ten {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration. | ||
Revision as of 00:33, 29 December 2016
Template:mpu CN5745-600 SP is a 64-bit deca-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates ten cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.