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Difference between revisions of "cavium/octeon plus/cn5740-800bg1217-ssp"
< cavium‎ | octeon plus

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| package 0 pins      = 1217
 
| package 0 pins      = 1217
 
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| package 0 width    = 40 mm
| package 0 length    =  
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| package 0 length    = 40 mm
 
| package 0 height    =  
 
| package 0 height    =  
 
| socket 0            = BGA-1217
 
| socket 0            = BGA-1217
 
| socket 0 type      = BGA
 
| socket 0 type      = BGA
 
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'''CN5740-800 SSP''' is a {{arch|64}} [[octa-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates eight {{cavium|cnMIPS|l=arch}} cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration.

Revision as of 23:20, 28 December 2016

Template:mpu CN5740-800 SSP is a 64-bit octa-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates eight cnMIPS cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.