From WikiChip
Difference between revisions of "cavium/octeon plus/cn5860-1000bg1521-nsp"
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| socket 0 type = BGA | | socket 0 type = BGA | ||
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+ | '''CN5860-1000 NSP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] network service microprocessor (NSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance network services software such as encryption, [[RegEx]], compression/decompression, and TCP acceleration. | ||
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|spi42=Yes | |spi42=Yes | ||
|spi42 ports=2 | |spi42 ports=2 | ||
+ | }} | ||
+ | |||
+ | == Hardware Accelerators == | ||
+ | {{accelerators | ||
+ | |encryption=Yes | ||
+ | |encryption type=DES, 3DES, AES-GCM, AES up to 256, SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI | ||
+ | |regex=Yes | ||
+ | |regex feature=32 Engines | ||
+ | |compression=Yes | ||
+ | |decompression=Yes | ||
+ | |tcp=Yes | ||
+ | |qos=Yes | ||
}} | }} |
Revision as of 22:37, 15 December 2016
Template:mpu CN5860-1000 NSP is a 64-bit hexadeca-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2007. This processor, which incorporates sixteen cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance network services software such as encryption, RegEx, compression/decompression, and TCP acceleration.
Cache
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Networking
Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
Hardware Accelerators
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Facts about "CN5860-1000 NSP - Cavium"