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Difference between revisions of "cavium/octeon plus/cn5860-600bg1521-exp"
< cavium‎ | octeon plus

Line 23: Line 23:
 
| series              = CN58xx
 
| series              = CN58xx
 
| locked              =  
 
| locked              =  
−
| frequency          = 600
+
| frequency          = 600 MHz
 +
| bus type            =
 +
| bus speed          =
 +
| bus rate            =
 +
| bus links          =
 +
| clock multiplier    =
  
 
| isa family          = MIPS
 
| isa family          = MIPS
Line 83: Line 88:
 
| socket 0            = BGA-1521
 
| socket 0            = BGA-1521
 
| socket 0 type      = BGA
 
| socket 0 type      = BGA
−
}} MHz
+
}}
−
| bus type            =  
+
 
−
| bus speed          =  
+
 
−
| bus rate            =  
+
== Cache ==
−
| bus links          =  
+
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
−
| clock multiplier    =
+
{{cache size
 +
|l1 cache=768 KiB
 +
|l1i cache=512 KiB
 +
|l1i break=16x32 KiB
 +
|l1i desc=64-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=16x16 KiB
 +
|l1d desc=64-way set associative
 +
|l2 cache=2 MiB
 +
|l2 break=1x2 MiB
 +
|l2 desc=8-way set associative
 +
}}

Revision as of 01:40, 15 December 2016

Template:mpu


Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$512 KiB
524,288 B
0.5 MiB
16x32 KiB64-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
16x16 KiB64-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB8-way set associative 
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5860-600bg1521-exp&oldid=31956"
Facts about "CN5860-600 EXP - Cavium"
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l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description64-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description64-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +