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Difference between revisions of "cavium/octeon plus/cn5850-600bg1521-exp"
< cavium‎ | octeon plus

(Created page with "{{cavium title|CN5850-600 EXP}} {{mpu | name = Cavium CN5850-600 EXP | no image = | image = octeon plus chip.png | image size...")
 
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| family              = OCTEON Plus
 
| family              = OCTEON Plus
−
| series              = 58xx
+
| series              = CN58xx
 
| locked              =  
 
| locked              =  
 
| frequency          = 600 MHz
 
| frequency          = 600 MHz

Revision as of 23:26, 14 December 2016

Template:mpu

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5850-600bg1521-exp&oldid=31833"
Facts about "CN5850-600 EXP - Cavium"
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CN5850-600 EXP - Cavium#package +
base frequency600 MHz (0.6 GHz, 600,000 kHz) +
core count12 +
designerCavium +
familyOCTEON Plus +
first announcedOctober 9, 2006 +
first launchedFebruary 2007 +
full page namecavium/octeon plus/cn5850-600bg1521-exp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size576 KiB (589,824 B, 0.563 MiB) +
l1d$ description64-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description64-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateFebruary 2007 +
main imageFile:octeon plus chip.png +
manufacturerTSMC +
market segmentNetwork +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN5850-600 EXP +
nameCavium CN5850-600 EXP +
packageFCBGA-1521 +
part numberCN5850-600BG1521-EXP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN58xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count12 +
word size64 bit (8 octets, 16 nibbles) +