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Difference between revisions of "cavium/octeon/cn3850-500bg1521-exp"
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The '''CN3850-500 EXP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
 
The '''CN3850-500 EXP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
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== Cache ==
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{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
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{{cache size
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|l1 cache=480 KiB
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|l1i cache=384 KiB
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|l1i break=12x32 KiB
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|l1i desc=64-way set associative
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|l1d cache=96 KiB
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|l1d break=12x8 KiB
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|l1d desc=64-way set associative
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|l1d policy=Write-through
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|l2 cache=1 MiB
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|l2 break=1x1 MiB
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|l2 desc=8-way set associative
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR2-800
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|ecc=Yes
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|max mem=16 GiB
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|controllers=1
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|channels=1
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|width=128 bit
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|max bandwidth=11.92 GiB/s
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|bandwidth schan=11.92 GiB/s
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}}
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== Expansions ==
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{{expansions
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|pcix width=64 bit
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|pcix clock=133.33 MHz
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|pcix rate=1,017.25 MiB/s
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|pcix extra=host or slave
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|uart=yes
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|uart ports=2
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|gp io=Yes
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}}
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== Networking ==
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{{network
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|mii opts=Yes
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|rgmii=yes
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|rgmii ports=8
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|spi opts=Yes
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|spi42=Yes
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|spi42 ports=2
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}}
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== Hardware Accelerators ==
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{{accelerators
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|regex=Yes
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|regex feature=16 Engines
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|compression=Yes
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|decompression=Yes
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|tcp=Yes
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|qos=Yes
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}}

Revision as of 22:26, 10 December 2016

Template:mpu The CN3850-500 EXP is a 64-bit dodeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates twelve cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$480 KiB
491,520 B
0.469 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB64-way set associative 
L1D$96 KiB
98,304 B
0.0938 MiB
12x8 KiB64-way set associativeWrite-through
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Max Mem16 GiB
Controllers1
Channels1
Width128 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width64 bit
Clock133.33 MHz
Rate1,017.25 MiB/s
Featureshost or slave
UART
Ports2
GP I/OYes


Networking

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 8)
SPI
SPI-4.2Yes (Ports: 2)

Hardware Accelerators

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
RegEx
RegExYes
Features16 Engines
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3850-500bg1521-exp&oldid=31485"
Facts about "CN3850-500 EXP - Cavium"
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has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
l1$ size480 KiB (491,520 B, 0.469 MiB) +
l1d$ description64-way set associative +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description64-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
supported memory typeDDR2-800 +