Revision as of 14:39, 9 December 2016

Template:mpu The CN3120-500 SCP is a 64-bit dual-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network processing such as high-performance I/O packet processing, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 80 KiB 81,920 B 0.0781 MiB L1I$ 64 KiB 65,536 B 0.0625 MiB 2x32 KiB 4-way set associative   L1D$ 16 KiB 16,384 B 0.0156 MiB 2x8 KiB 64-way set associative Write-through L2$ 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB     1x256 KiB 8-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR2-667 Supports ECC Yes Max Mem 4 GiB Controllers 1 Channels 1 Width 64 bit Max Bandwidth 4.97 GiB/s 5,089.28 MiB/s 5.336 GB/s 5,336.497 MB/s 0.00485 TiB/s 0.00534 TB/s Bandwidth Single 4.97 GiB/s

Optional low-latency controller for content-based processing and meta data

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR2-667 Supports ECC Yes Max Mem 2 GiB Controllers 1 Channels 1 Width 16 bit Max Bandwidth 1.24 GiB/s 1,269.76 MiB/s 1.331 GB/s 1,331.44 MB/s 0.00121 TiB/s 0.00133 TB/s Bandwidth Single 1.24 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
	PCI-X Width 32 bit Clock 100 MHz Rate 381.5 MiB/s USB Revision 2.0 Ports 1 Rate 60 MB/s Features host / PHY UART Ports 2 GP I/O Yes

Networking

[Edit/Modify Network Info]

	Networking
	MII GMII Yes (Ports: 1) RGMII Yes (Ports: 3) TDM/PCM Yes

Features

Hardware acceleration units:

• Packet I/O processing
• QoS
• TCP Acceleration

Block diagram

Datasheet

• OCTEON CN31XX Single- and Dual-Core Product Briefn