Semiconductor & Computer Engineering
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Difference between revisions of "cavium/octeon/cn3110-500bg868-cp"
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|l1d policy=Write-through | |l1d policy=Write-through | ||
|l2 cache=256 KiB | |l2 cache=256 KiB | ||
| − | |l2 break= | + | |l2 break=1x256 KiB |
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
}} | }} | ||
Revision as of 12:42, 9 December 2016
Template:mpu The CN3110-500 SCP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates a cnMIPS core, operates at 500. This processor includes a number of hardware accelerators for network processing such as high-performance I/O packet processing, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "CN3110-500 CP - Cavium"
| l1$ size | 40 KiB (40,960 B, 0.0391 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |