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Difference between revisions of "cavium/octeon/cn3120-400bg868-exp"
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+ | The '''CN3120-400 EXP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware accelerators for network processing such as [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. |
Revision as of 03:14, 9 December 2016
Template:mpu The CN3120-400 EXP is a 64-bit dual-core MIPS communication microprocessor designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware accelerators for network processing such as compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Facts about "CN3120-400 EXP - Cavium"
l1$ size | 80 KiB (81,920 B, 0.0781 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |