From WikiChip
Difference between revisions of "cavium/octeon/cn3110-400bg868-nsp"
< cavium‎ | octeon

(Created page with "{{cavium title|CN3110-400 NSP}} {{mpu | name = Cavium CN3110-400 NSP | no image = | image = octeon cn31xx.png | image size =...")
 
Line 89: Line 89:
 
| socket 0 type      =  
 
| socket 0 type      =  
 
}}
 
}}
 +
The '''CN3110-400 NSP''' is a {{arch|64}} [[single-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 400 MHz. This processor includes a number of hardware accelerators for network services such as [[encryption]], [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Revision as of 02:34, 9 December 2016

Template:mpu The CN3110-400 NSP is a 64-bit single-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 400 MHz. This processor includes a number of hardware accelerators for network services such as encryption, compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3110-400bg868-nsp&oldid=30871"
Facts about "CN3110-400 NSP - Cavium"
RDF feed
l1$ size40 KiB (40,960 B, 0.0391 MiB) +
l1d$ description64-way set associative +
l1d$ size8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description4-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +