From WikiChip
Difference between revisions of "cavium/octeon/cn3010-400bg525-cp"
< cavium‎ | octeon

(Created page with "{{cavium title|CN3010-400 CP}} {{mpu | name = Cavium CN3010-400 CP | no image = | image = cn3005-15.png | image size = | cap...")
 
Line 89: Line 89:
 
| socket 0 type      =  
 
| socket 0 type      =  
 
}}
 
}}
 +
The '''CN3010-400 CP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 400 MHz and dissipates 3 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the {{\\|cn3005-400bg350-cp|CN3015 equivalent}} as well as support for TDM/PCM (VoIP support).

Revision as of 19:19, 8 December 2016

Template:mpu The CN3010-400 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 400 MHz and dissipates 3 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the CN3015 equivalent as well as support for TDM/PCM (VoIP support).

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3010-400bg525-cp&oldid=30751"
Facts about "CN3010-400 CP - Cavium"
RDF feed
base frequency400 MHz (0.4 GHz, 400,000 kHz) +
core count1 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3010-400bg525-cp +
has ecc memory supporttrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size24 KiB (24,576 B, 0.0234 MiB) +
l1d$ description64-way set associative +
l1d$ size8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description2-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description4-way set associative +
l2$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
ldateMay 1, 2006 +
main imageFile:cn3005-15.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth1.986 GiB/s (2,033.664 MiB/s, 2.132 GB/s, 2,132.451 MB/s, 0.00194 TiB/s, 0.00213 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3010-400 CP +
nameCavium CN3010-400 CP +
part numberCN3010-400BG525-CP +
power dissipation3 W (3,000 mW, 0.00402 hp, 0.003 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3000 +
smp max ways1 +
supported memory typeDDR2-533 +
technologyCMOS +
thread count1 +
word size64 bit (8 octets, 16 nibbles) +