From WikiChip
Difference between revisions of "cavium/octeon/cn3005-500bg350-scp"
< cavium‎ | octeon

(Created page with "{{cavium title|CN3005 500 MHz SCP}} {{mpu | name = Cavium CN3005-500 SCP | no image = cn3005-15.png | image = | image size =...")
 
Line 1: Line 1:
−
{{cavium title|CN3005 500 MHz SCP}}
+
{{cavium title|CN3005-500 SCP}}
 
{{mpu
 
{{mpu
 
| name                = Cavium CN3005-500 SCP
 
| name                = Cavium CN3005-500 SCP

Revision as of 05:32, 8 December 2016

Template:mpu The CN3005-500 SCP is a 64-bit single-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2005. This processor, which incorporates a single cnMIPS core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration.

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3005-500bg350-scp&oldid=30603"