Semiconductor & Computer Engineering
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Difference between revisions of "amd/duron/dhm0800avs1bm"
(Created page with "{{amd title|Duron 800 (Camaro)}} {{mpu | name = Duron 800 | no image = Yes | image = | image size = | caption =...") |
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| bus rate = 200 MT/s | | bus rate = 200 MT/s | ||
| clock multiplier = 8 | | clock multiplier = 8 | ||
| − | | cpuid = | + | | cpuid = 660 |
| microarch = K7 | | microarch = K7 | ||
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| socket 0 type = PGA-462 | | socket 0 type = PGA-462 | ||
}} | }} | ||
| + | The '''Mobile Duron 800''' based on the {{amd|Morgan|l=core}} (Camaro) core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2001. This model was part of the second generation of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} on a [[180 nm process]], this MPU operated at 800 MHz with a bus capable of 200 MT/s. | ||
Revision as of 15:30, 24 October 2016
Template:mpu The Mobile Duron 800 based on the Morgan (Camaro) core was a 32-bit x86 microprocessor developed by AMD and introduced in 2001. This model was part of the second generation of the Duron family. Designed based on AMD's K7 on a 180 nm process, this MPU operated at 800 MHz with a bus capable of 200 MT/s.
Facts about "Duron 800 (Camaro) - AMD"
| has feature | Halt State + and Sleep State + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |