Semiconductor & Computer Engineering
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Difference between revisions of "amd/k6/amd-k6-200alr"
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== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}} | {{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}} | ||
| − | [[L2$]] can be 256 | + | [[L2$]] can be 256 KiB to 1 MiB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip. |
{{cache info | {{cache info | ||
| − | |l1i cache=32 | + | |l1i cache=32 KiB |
| − | |l1i break=1x32 | + | |l1i break=1x32 KiB |
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=32 | + | |l1d cache=32 KiB |
| − | |l1d break=1x32 | + | |l1d break=1x32 KiB |
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
|l1d extra= | |l1d extra= | ||
Revision as of 00:18, 21 September 2016
Template:mpu AMD-K6-200ALR was a 32-bit x86 microprocessor designed by AMD and introduced in early 1997. This chip, which was based on AMD's new K6 microarchitecture, operated at 200 MHz and dissipated a maximum of 20 W.
Contents
Cache
- Main article: K6 § Cache
L2$ can be 256 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
Documents
DataSheet
- AMD-K6 MMX Enhanced Processor Multimedia Technology; Publication #20695 Revision E/0; June 1997
Facts about "AMD-K6-200ALR - AMD"
| base frequency | 199.99 MHz (0.2 GHz, 199,990 kHz) + |
| bus rate | 66.66 MT/s (0.0667 GT/s, 66,660 kT/s) + |
| bus speed | 66.66 MHz (0.0667 GHz, 66,660 kHz) + |
| bus type | FSB + |
| clock multiplier | 3 + |
| core count | 1 + |
| core family | 5 + |
| core model | 6 + |
| core name | 6k86 + |
| core voltage | 2.9 V (29 dV, 290 cV, 2,900 mV) + |
| core voltage tolerance | 5% + |
| cpuid | 560 + |
| designer | AMD + |
| die area | 162 mm² (0.251 in², 1.62 cm², 162,000,000 µm²) + |
| family | K6 + |
| first announced | May 1997 + |
| first launched | May 1997 + |
| full page name | amd/k6/amd-k6-200alr + |
| has locked clock multiplier | false + |
| instance of | microprocessor + |
| io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
| io voltage tolerance | 5% + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| ldate | May 1997 + |
| manufacturer | AMD + |
| market segment | Desktop + |
| max case temperature | 343.15 K (70 °C, 158 °F, 617.67 °R) + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max storage temperature | 423.15 K (150 °C, 302 °F, 761.67 °R) + |
| microarchitecture | K6 + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min storage temperature | 208.15 K (-65 °C, -85 °F, 374.67 °R) + |
| model number | AMD-K6-200ALR + |
| name | AMD-K6-200ALR + |
| part number | AMD-K6-200ALR + |
| power dissipation | 20 W (20,000 mW, 0.0268 hp, 0.02 kW) + |
| process | 350 nm (0.35 μm, 3.5e-4 mm) + |
| series | Desktop K6 + |
| smp max ways | 1 + |
| technology | CMOS + |
| thread count | 1 + |
| transistor count | 8,800,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |