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Difference between revisions of "intel/xeon e3/e3-1284l v3"
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== Cache == | == Cache == | ||
| + | {{main|intel/microarchitectures/haswell#Memory_Hierarchy|l1=Haswell § Cache}} | ||
This specific microprocessor includes the [[has feature::Crystal Well]] cache. | This specific microprocessor includes the [[has feature::Crystal Well]] cache. | ||
{{cache info | {{cache info | ||
| − | |l1i cache=128 | + | |l1i cache=128 KiB |
| − | |l1i break=4x32 | + | |l1i break=4x32 KiB |
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
|l1i extra=(per core, write-back) | |l1i extra=(per core, write-back) | ||
| − | |l1d cache=128 | + | |l1d cache=128 KiB |
| − | |l1d break=4x32 | + | |l1d break=4x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d extra=(per core, write-back) | |l1d extra=(per core, write-back) | ||
| − | |l2 cache=1 | + | |l2 cache=1 MiB |
| − | |l2 break=4x256 | + | |l2 break=4x256 KiB |
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
|l2 extra=(per core, write-back) | |l2 extra=(per core, write-back) | ||
|l3 cache=6 MiB | |l3 cache=6 MiB | ||
| − | |l3 desc=shared | + | |l3 desc=12-way set associative |
| + | |l3 extra=(shared) | ||
|l4 cache=128 MiB | |l4 cache=128 MiB | ||
|l4 desc=16-way set associative | |l4 desc=16-way set associative | ||
Revision as of 23:13, 20 September 2016
Template:mpu The Intel Xeon E3-1284L v3 is a quad core 64-bit server microprocessor released by Intel in 2014. The microprocessor is based on the Haswell microarchitecture. This MPU includes the Intel Iris Pro 5200 integrated graphic and features the 128 MB L4$ Crystal Well cache.
Contents
Cache
- Main article: Haswell § Cache
This specific microprocessor includes the Crystal Well cache.
| Cache Info [Edit Values] | ||
| L1I$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
| L1D$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
| L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB |
4x256 KiB 8-way set associative (per core, write-back) |
| L3$ | 6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB |
12-way set associative (shared) |
| L4$ | 128 MiB 131,072 KiB 134,217,728 B 0.125 GiB |
16-way set associative (see Crystal Well) |
Graphics
| Integrated Graphic Information | |
| GPU | Intel Iris Pro Graphics 5200 |
| Displays | 3 |
| Frequency | 200 MHz 0.2 GHz
200,000 KHz |
| Max frequency | 750 MHz 0.75 GHz
750,000 KHz |
| Max memory | 1000 MB "MB" is not declared as a valid unit of measurement for this property.
|
| Output | DisplayPort, Embedded DisplayPort, HDMI, VGA |
Memory controller
| Integrated Memory Controller | |
| Type | DDR3L-1333, DDR3L-1600 |
| Controllers | 1 |
| Channels | 2 |
| ECC Support | Yes |
| Max bandwidth | 25,600 MB/s |
| Max memory | 32,768 MB |
Features
Facts about "Xeon E3-1284L v3 - Intel"
| has feature | Crystal Well + and integrated gpu + |
| integrated gpu | Intel Iris Pro Graphics 5200 + |
| integrated gpu base frequency | 200 MHz (0.2 GHz, 200,000 KHz) + |
| integrated gpu max frequency | 750 MHz (0.75 GHz, 750,000 KHz) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 12-way set associative + |
| l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
| l4$ description | 16-way set associative + |
| l4$ size | 128 MiB (131,072 KiB, 134,217,728 B, 0.125 GiB) + |