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Difference between revisions of "intel/core i3/6120t"
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{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
{{cache info | {{cache info | ||
− | |l1i cache=64 | + | |l1i cache=64 KiB |
− | |l1i break=2x32 | + | |l1i break=2x32 KiB |
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
|l1i extra=(per core, write-back) | |l1i extra=(per core, write-back) | ||
− | |l1d cache=64 | + | |l1d cache=64 KiB |
− | |l1d break=2x32 | + | |l1d break=2x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d extra=(per core, write-back) | |l1d extra=(per core, write-back) | ||
− | |l2 cache=512 | + | |l2 cache=512 KiB |
− | |l2 break=2x256 | + | |l2 break=2x256 KiB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
|l2 extra=(per core, write-back) | |l2 extra=(per core, write-back) |
Revision as of 22:32, 20 September 2016
Template:mpu
Core i3-6120T is a 64-bit dual-core low-end performance microprocessor set to be introduced by Intel in 2016.
Cache
- Main article: Skylake § Cache
Cache Info [Edit Values] | ||
L1I$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB 8-way set associative (per core, write-back) |
L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB |
2x256 KiB 4-way set associative (per core, write-back) |
L3$ | 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB |
shared |
Expansions
Features
Facts about "Core i3-6120T - Intel"
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | shared + |
l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |