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Difference between revisions of "amd/k6-2/k6-2-400ahx"
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'''K6-2/400AHX''' was a {{arch|32}} [[x86]] {{amd|microarchitectures/k6-2|K6-2}}-based microprocessor designed and manufactured in [[1998]] by [[AMD]]. Manufactured using a [[0.25 µm process]], this MPU operated at 400 MHz with a [[FSB]] of 100 MHz consumed 17.7 W. Note that {{\\|K6-2-400AHX-66|K6-2/400AHX-66}} is an identical model with a multiplier of 6 instead of 4 designed to support a 66 MHz bus instead. | '''K6-2/400AHX''' was a {{arch|32}} [[x86]] {{amd|microarchitectures/k6-2|K6-2}}-based microprocessor designed and manufactured in [[1998]] by [[AMD]]. Manufactured using a [[0.25 µm process]], this MPU operated at 400 MHz with a [[FSB]] of 100 MHz consumed 17.7 W. Note that {{\\|K6-2-400AHX-66|K6-2/400AHX-66}} is an identical model with a multiplier of 6 instead of 4 designed to support a 66 MHz bus instead. | ||
| + | |||
| + | == Cache == | ||
| + | {{main|amd/microarchitectures/k6-2#Memory_Hierarchy|l1=K6-2 § Cache}} | ||
| + | [[L2$]] can be 512 KB to 2 MB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip. | ||
| + | {{cache info | ||
| + | |l1i cache=32 KB | ||
| + | |l1i break=1x32 KB | ||
| + | |l1i desc=2-way set associative | ||
| + | |l1i extra= | ||
| + | |l1d cache=32 KB | ||
| + | |l1d break=1x32 KB | ||
| + | |l1d desc=2-way set associative | ||
| + | |l1d extra= | ||
| + | |l2 cache= | ||
| + | |l2 break= | ||
| + | |l2 desc= | ||
| + | |l2 extra= | ||
| + | |l3 cache= | ||
| + | |l3 break= | ||
| + | |l3 desc= | ||
| + | |l3 extra= | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This SoC has no integrated graphics processing unit. | ||
| + | |||
| + | == Features == | ||
| + | {{mpu features | ||
| + | | mmx = true | ||
| + | | 3dnow = true | ||
| + | }} | ||
| + | * Auto-power down state | ||
| + | * Stop clock state | ||
Revision as of 21:42, 3 August 2016
Template:mpu K6-2/400AHX was a 32-bit x86 K6-2-based microprocessor designed and manufactured in 1998 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 400 MHz with a FSB of 100 MHz consumed 17.7 W. Note that K6-2/400AHX-66 is an identical model with a multiplier of 6 instead of 4 designed to support a 66 MHz bus instead.
Cache
- Main article: K6-2 § Cache
L2$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L2$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
| L1D$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
Facts about "K6-2/400AHX - AMD"
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |