From WikiChip
Difference between revisions of "intel/core i3/6120t"
| Line 100: | Line 100: | ||
| uart = | | uart = | ||
| gp io = | | gp io = | ||
| + | }} | ||
| + | |||
| + | == Features == | ||
| + | {{mpu features | ||
| + | | em64t = Yes | ||
| + | | nx = Yes | ||
| + | | txt = | ||
| + | | tsx = | ||
| + | | vpro = | ||
| + | | ht = Yes | ||
| + | | tbt1 = | ||
| + | | tbt2 = | ||
| + | | bpt = | ||
| + | | vt-x = Yes | ||
| + | | vt-d = Yes | ||
| + | | ept = Yes | ||
| + | | mmx = Yes | ||
| + | | sse = Yes | ||
| + | | sse2 = Yes | ||
| + | | sse3 = Yes | ||
| + | | ssse3 = Yes | ||
| + | | sse4 = Yes | ||
| + | | sse4.1 = Yes | ||
| + | | sse4.2 = Yes | ||
| + | | aes = Yes | ||
| + | | pclmul = Yes | ||
| + | | avx = Yes | ||
| + | | avx2 = Yes | ||
| + | | bmi = Yes | ||
| + | | bmi1 = Yes | ||
| + | | bmi2 = Yes | ||
| + | | f16c = Yes | ||
| + | | fma3 = Yes | ||
| + | | mpx = Yes | ||
| + | | sgx = Yes | ||
| + | | eist = Yes | ||
| + | | secure key = Yes | ||
| + | | os guard = Yes | ||
| + | | intel at = | ||
}} | }} | ||
Revision as of 13:43, 13 May 2016
Template:mpu
Core i3-6120T is a 64-bit dual-core low-end microprocessor set to be introduced by Intel in 2016.
Cache
- Main article: Skylake § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
2x32 KB 8-way set associative (per core, write-back) |
| L1D$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
2x32 KB 8-way set associative (per core, write-back) |
| L2$ | 512 KB "KB" is not declared as a valid unit of measurement for this property. |
2x256 KB 4-way set associative (per core, write-back) |
| L3$ | 3 MB "MB" is not declared as a valid unit of measurement for this property. |
shared |
Expansions
Features
Facts about "Core i3-6120T - Intel"
| l1d$ description | 8-way set associative + |
| l1i$ description | 8-way set associative + |
| l2$ description | 4-way set associative + |
| l3$ description | shared + |