From WikiChip
Difference between revisions of "intel/xeon e3/e3-1240 v5"
< intel

Line 114: Line 114:
 
| bandwidth dchan    =  
 
| bandwidth dchan    =  
 
| max memory        = 64 GB
 
| max memory        = 64 GB
 +
}}
 +
 +
== Expansions ==
 +
{{mpu expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 16
 +
| pcie config        = 1x16
 +
| pcie config 1      = 2x8
 +
| pcie config 2      = 1x8+2x4
 +
| usb revision      =
 +
| usb revision 2    =
 +
| usb revision N    =
 +
| usb ports          =
 +
| sata ports        =
 +
| integrated lan    =
 +
| uart              =
 
}}
 
}}

Revision as of 11:11, 4 May 2016

Template:mpu The Xeon E3-1240 V5 is an entry-level workstations and servers 64-bit x86 quad-core microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.5 GHz with turbo boost of 3.9 GHz. The E3-1240 V5 has a TDP of 80 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has no integrated graphics processor.

Cache

Main article: Skylake § Cache
Cache Info [Edit Values]
L1I$ 128 KB
"KB" is not declared as a valid unit of measurement for this property.
 		4x32 KB 8-way set associative (per core, write-back)
L1D$ 128 KB
"KB" is not declared as a valid unit of measurement for this property.
 		4x32 KB 8-way set associative (per core, write-back)
L2$ 1 MB
"MB" is not declared as a valid unit of measurement for this property.
 		4x256 KB 4-way set associative (per core)
L3$ 8 MB
"MB" is not declared as a valid unit of measurement for this property.
 		4x2 MB

Graphics

This chip has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600, DDR3L-RS1333, DDR3L-RS1600, DDR4-1866, DDR4-2133, DDR4-RS1866, DDR4-RS2133
Controllers 1
Channels 2
ECC Support Yes
Max bandwidth 34.1 GB/s
Max memory 64 GB

Expansions

Template:mpu expansions

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e3/e3-1240_v5&oldid=17853"
Facts about "Xeon E3-1240 v5 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E3-1240 v5 - Intel#package + and Xeon E3-1240 v5 - Intel#io +
base frequency3,500 MHz (3.5 GHz, 3,500,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetSunrise Point +
clock multiplier35 +
core count4 +
core family6 +
core model94 +
core nameSkylake DT +
core steppingR0 +
core voltage (max)1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)0.55 V (5.5 dV, 55 cV, 550 mV) +
cpuid506E3 +
designerIntel +
die area122 mm² (0.189 in², 1.22 cm², 122,000,000 µm²) +
familyXeon E3 +
first announcedOctober 19, 2015 +
first launchedOctober 19, 2015 +
full page nameintel/xeon e3/e3-1240 v5 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Secure Key Technology +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Trusted Execution Technology +, Intel vPro Technology +, Transactional Synchronization Extensions +, OS Guard +, Extended Page Tables +, Memory Protection Extensions + and Software Guard Extensions +
has intel enhanced speedstep technologytrue +
has intel secure key technologytrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
last orderOctober 26, 2018 +
last shipmentApril 12, 2019 +
ldateOctober 19, 2015 +
main imageFile:skylake dt (front).png +
manufacturerIntel +
market segmentServer +
max cpu count1 +
max junction temperature373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes16 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureSkylake +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberE3-1240 v5 +
nameXeon E3-1240 v5 +
packageFCLGA-1151 +
part numberCM8066201921715 + and BX80662E31240V5 +
platformGreenlow +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 282.00 (€ 253.80, £ 228.42, ¥ 29,139.06) +
s-specSR2CM + and SR2LD +
seriesE3-1200 v5 +
smp max ways1 +
socketLGA-1151 +
supported memory typeDDR3L-1600 + and DDR4-2133 +
tdp80 W (80,000 mW, 0.107 hp, 0.08 kW) +
technologyCMOS +
thread count8 +
turbo frequency (1 core)3,900 MHz (3.9 GHz, 3,900,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +
x86/has software guard extensionstrue +