From WikiChip
Difference between revisions of "Template:planar comp header"

(fixed)
 
Line 1: Line 1:
{| class="wikitable" style="float:left; margin:0; margin-right:-1px; font-family: monospace;"
+
{| class="wikitable" style="float:left; margin:0; margin-right:-1px; font-family: monospace; width: 25%;"
 
  |-
 
  |-
 
  ! colspan="2" |  
 
  ! colspan="2" |  
Line 7: Line 7:
 
  ! style="text-align: right;" colspan="2" | 1st Production
 
  ! style="text-align: right;" colspan="2" | 1st Production
 
  |-
 
  |-
  ! style="text-align: center;" rowspan="3" | Lithography || style="text-align: right;" | Lithography
+
  ! style="text-align: center;" rowspan="3" | Litho-<br>graphy || style="text-align: right;" | Lithography
 
  |-
 
  |-
 
  ! style="text-align: right;" | Immersion
 
  ! style="text-align: right;" | Immersion
Line 17: Line 17:
 
  ! style="text-align: right;" | Size
 
  ! style="text-align: right;" | Size
 
  |-
 
  |-
  ! style="text-align: center;" rowspan="2" | Transistor || style="text-align: right;" | Type
+
  ! style="text-align: center;" rowspan="2" | Tran-<br>sistor || style="text-align: right;" | Type
 
  |-
 
  |-
 
  ! style="text-align: right;" | Voltage
 
  ! style="text-align: right;" | Voltage
Line 31: Line 31:
 
  ! style="text-align: right;" colspan="2" | Minimum Metal Pitch (MMP)
 
  ! style="text-align: right;" colspan="2" | Minimum Metal Pitch (MMP)
 
  |-
 
  |-
  ! style="text-align: right;" rowspan="3" | SRAM bitcell || style="text-align: right;" | High-Perf (HP)
+
  ! style="text-align: right;" rowspan="3" | SRAM <br>bitcell || style="text-align: right;" | High-Perf (HP)
 
  |-
 
  |-
 
  ! style="text-align: right;" | High-Density (HD)
 
  ! style="text-align: right;" | High-Density (HD)
Line 37: Line 37:
 
  ! style="text-align: right;" | Low-Voltage (LV)
 
  ! style="text-align: right;" | Low-Voltage (LV)
 
  |-
 
  |-
  ! style="text-align: right;" rowspan="3" | DRAM bitcell || style="text-align: right;" | eDRAM
+
  ! style="text-align: right;" rowspan="3" | DRAM <br>bitcell || style="text-align: right;" | eDRAM
 
|}
 
|}

Latest revision as of 17:36, 19 March 2025

 
Process Name
1st Production
Litho-
graphy
Lithography
Immersion
Exposure
Wafer Type
Size
Tran-
sistor
Type
Voltage
Metal Layers
 
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM
bitcell
High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM
bitcell
eDRAM