Semiconductor & Computer Engineering
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Verilog has a few iterations: Verilog 95, Verilog 2001, Verilog 2005 and SystemVerilog. All of the new revisions have added something new and useful. | Verilog has a few iterations: Verilog 95, Verilog 2001, Verilog 2005 and SystemVerilog. All of the new revisions have added something new and useful. | ||
The latest update was a SystemVerilog(SV). It was declared that SV is a superset of Verilog, and it is backwards compatible with it. That means that all of Verilog code can be run in SystemVerilog simulators and design tools. Only thing that SV added is better Verification methodology like UVM and OVM style of testbenches. | The latest update was a SystemVerilog(SV). It was declared that SV is a superset of Verilog, and it is backwards compatible with it. That means that all of Verilog code can be run in SystemVerilog simulators and design tools. Only thing that SV added is better Verification methodology like UVM and OVM style of testbenches. | ||
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== Syntax == | == Syntax == | ||
Verilog is a static, weakly typed style language similar to C in some aspects. It is case sensitive(meaning that there is difference between "a" and "A"), has preprocessor and has control flow keywords(allowing for if,else, for, while etc. statements to be implemented). | Verilog is a static, weakly typed style language similar to C in some aspects. It is case sensitive(meaning that there is difference between "a" and "A"), has preprocessor and has control flow keywords(allowing for if,else, for, while etc. statements to be implemented). | ||
The basic look of every module is like the following: | The basic look of every module is like the following: | ||
Revision as of 11:43, 25 March 2018
INTRODUCTION
Verilog is a HDL(Hardware Description Language) and HVL(Hardware Verification Language) made for describing, modeling and simulating circuits. It is used at early front-end IC design.
Verilog has a few iterations: Verilog 95, Verilog 2001, Verilog 2005 and SystemVerilog. All of the new revisions have added something new and useful. The latest update was a SystemVerilog(SV). It was declared that SV is a superset of Verilog, and it is backwards compatible with it. That means that all of Verilog code can be run in SystemVerilog simulators and design tools. Only thing that SV added is better Verification methodology like UVM and OVM style of testbenches.
Syntax
Verilog is a static, weakly typed style language similar to C in some aspects. It is case sensitive(meaning that there is difference between "a" and "A"), has preprocessor and has control flow keywords(allowing for if,else, for, while etc. statements to be implemented).
The basic look of every module is like the following: