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Difference between revisions of "intel/core m/5y51"
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| pcie lanes        = 12

Revision as of 14:54, 13 December 2017

Template:mpu The Core M 5Y51 is an ultra-low power dual-core 64-bit x86 microprocessor introduced by Intel in 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.6 GHz. The 5Y51 has a configurable TDP-down of 3.5 W @ 600 MHz and a configurable TDP-up of 6 W @ 1.3 GHz. This chip, which is manufactured in 14 nm process based on the Broadwell microarchitecture and incorporates Intel's HD Graphics 5300 Gen8 GPU clocked at 300 MHz with turbo frequency of 900 MHz.

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core)
L1D$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core)
L2$ 512 MiB
524,288 KiB
536,870,912 B
0.5 GiB
2x256 KiB 8-way set associative (per core)
L3$ 4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
2x2 MiB (shared LLC)

Graphics

Integrated Graphic Information
GPU Intel HD Graphics 5300
Device ID 0x161E
Execution Units 24
Displays 3
Frequency 300 MHz
0.3 GHz
300,000 KHz
Max frequency 900 MHz
0.9 GHz
900,000 KHz
Max memory 16 GiB
16,384 MiB
16,777,216 KiB
17,179,869,184 B
Output DisplayPort, Embedded DisplayPort, HDMI
DirectX 11.2
OpenGL 4.3
OpenCL 2.0
HDMI 1.4a
DP 1.2
eDP 1.3
Max HDMI Res 2560x1600 @60 Hz, 4096x2304 @24 Hz
Max DVI Res 1920x1200 @60 Hz
Max DP Res 2560x1600 @60 Hz, 3840x2160 @60 Hz
Max eDP Res 2560x1600 @60 Hz, 3840x2160 @60 Hz
Intel Quick Sync Video
Intel InTru 3D
Intel Insider
Intel WiDi (Wireless Display)
Intel Flexible Display Interface (FDI)
Intel Clear Video
  • AVC/H.264 Encode
  • MPEG2 Encode
  • MVC HW Encode
  • JPEG/MJPEG Hardware Encode
  • Blu-ray* Disc Playback
  • AVC/H.264, MPEG2, VC1 Decode

Memory controller

Integrated Memory Controller
Type LPDDR3-1333, LPDDR3-1600, DDR3L-1600, DDR3L-RS1600
Controllers 1
Channels 2
ECC Support No
Max bandwidth 25.6 GB/s
Max memory 16 GB

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes12
Configs6x1, 3x4


Features

Drivers

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_m/5y51&oldid=69860"
Facts about "Core M 5Y51"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Core M 5Y51#io +
device id0x161E +
drivers urlhttps://downloadcenter.intel.com/product/94028 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureintegrated gpu +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology + and Extended Page Tables +
has intel enhanced speedstep technologytrue +
has intel turbo boost technology 2 0true +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
integrated gpuIntel HD Graphics 5300 +
integrated gpu base frequency300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu max frequency900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size512 MiB (524,288 KiB, 536,870,912 B, 0.5 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
max pcie lanes12 +