Difference between revisions of "intel/xeon e5/e5-2650 v4"

Revision as of 14:48, 13 December 2017

Template:mpu The Xeon E5-2650 v4 is a 64-bit dodeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for advanced 2S environments (1U square form factor). Operating at 2.2 GHz with a turbo boost frequency of 2.9 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache

Cache Info [Edit Values]
L1I$	384 KiB 393,216 B 0.375 MiB	12x32 KiB 8-way set associative (per core, write-back)
L1D$	384 KiB 393,216 B 0.375 MiB	12x32 KiB 8-way set associative (per core, write-back)
L2$	3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB	12x256 KiB 8-way set associative (per core, write-back)
L3$	30 MiB 30,720 KiB 31,457,280 B 0.0293 GiB	12x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type	DDR4-2400
Controllers	1
Channels	4
ECC Support	Yes
Max bandwidth	71.53 GiB/s
Bandwidth (single)	17.88 GiB/s
Bandwidth (dual)	35.76 GiB/s
Max memory	1,536 GiB
Physical Address Extensions	46 bit

Expansions

Template:mpu expansions

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
F16C	16-bit Floating Point Conversion

NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions

Benchmarks

[Edit Benchmarks]

Test: SPEC CPU2017
Tested: 2017-10-03 11:47:03-0400
Chips: 2, Cores: 24, Copies: 48

Vendor: Inspur Corporation
System: Inspur NF5170M4 (Intel Xeon E5-2650 v4)

SPECrate2017_int_base: 105

SPECrate2017_int_peak: 112

@@ Line 134: / Line 134: @@
 == Features ==
-{{mpu features
+{{x86 features
 | em64t       = Yes
 | nx          = Yes

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon E5-2650 v4 - Intel#io + and Xeon E5-2650 v4 - Intel +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links	2 +
bus rate	9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) +
bus speed	4,800 MHz (4.8 GHz, 4,800,000 kHz) +
bus type	QPI +
chipset	C610 Series +
clock multiplier	22 +
core count	12 +
core family	6 +
core model	4F +
core name	Broadwell EP +
core stepping	M0 +
core voltage	1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid	406F1 +
designer	Intel +
die area	306.18 mm² (0.475 in², 3.062 cm², 306,180,000 µm²) +
family	Xeon E5 +
first announced	June 20, 2016 +
first launched	June 20, 2016 +
full page name	intel/xeon e5/e5-2650 v4 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
io voltage	1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance	3% +
isa	x86-64 +
isa family	x86 +
l1d$ description	8-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) +
l1i$ description	8-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	8-way set associative +
l2$ size	3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ description	20-way set associative +
l3$ size	30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) +
ldate	June 20, 2016 +
manufacturer	Intel +
market segment	Server +
max case temperature	353.15 K (80 °C, 176 °F, 635.67 °R) +
max cpu count	2 +
max memory	1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes	40 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Broadwell +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	E5-2650 v4 +
name	Xeon E5-2650 v4 +
part number	CM8066002031103 + and BX80660E52650V4 +
platform	Grantley EP 2S +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,166.00 (€ 1,049.40, £ 944.46, ¥ 120,482.78) +
s-spec	SR2N3 +
s-spec (qs)	QK8Y +
series	E5-2000 +
smp max ways	2 +
tdp	105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technology	CMOS +
thread count	24 +
transistor count	4,700,000,000 +
turbo frequency (10 cores)	2,500 MHz (2.5 GHz, 2,500,000 kHz) +
turbo frequency (11 cores)	2,500 MHz (2.5 GHz, 2,500,000 kHz) +
turbo frequency (12 cores)	2,500 MHz (2.5 GHz, 2,500,000 kHz) +
turbo frequency (1 core)	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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