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Difference between revisions of "mediatek/helio/p30"
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Revision as of 15:08, 10 September 2017
Template:mpu Helio P30 is a mid-range performance 64-bit octa-core ARM LTE system on a chip designed by MediaTek set to launch in late 2017. This SoC, which is fabricated on TSMC's 16 nm process, incorporates eight Cortex-A53 cores with four little cores operating at up to 1.65 GHz and four big cores operating at up to 2.3 GHz. The Helio P30 supports up to 6 GiB of dual-channel LPDDR4X-3200 memory and incorporates a modem supporting LTE User Equipment (UE) category 7 (DL)/13 (UL).
Cache
- Main article: Cortex-A53 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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This section is empty; you can help add the missing info by editing this page. |
Memory controller
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Integrated Memory Controller
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Graphics
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Integrated Graphics Information
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Hardware Accelerated Video Capabilities | ||
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Codec | Encode | Decode |
MPEG-4 AVC (H.264) | @ 30 FPS | @ 30 FPS |
HEVC (H.265) | ✘ | @ 30 FPS |
VP9 | @ 30 FPS | @ 30 FPS |
Wireless
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Cellular | |||||||
4G |
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Camera
- 25MP (single), 16MP+16MP (dual)
- 3840 x 2160 max recording resolution @ 30 FPS
- color+mono, wide+tele zoom with real-time depth engine
Utilizing devices
This list is incomplete; you can help by expanding it.
Facts about "Helio P30 - MediaTek"