Semiconductor & Computer Engineering
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Difference between revisions of "mediatek/helio/mt6763t"
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'''Helio P23''' is a mid-range performance {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] set to launch in late [[2017]]. This SoC, which is fabricated on [[TSMC]]'s [[16 nm process]], incorporates eight {{armh|Cortex-A53|l=arch}} cores with four [[little cores]] operating at up to 1.65 GHz and four [[big cores]] operating at up to 2.3 GHz. The Helio P23 supports up to 6 GiB of dual-channel LPDDR4X-3200 memory and incorporates a modem supporting [[LTE]] User Equipment (UE) category 6 and 7 (DL)/13 (UL). | '''Helio P23''' is a mid-range performance {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] set to launch in late [[2017]]. This SoC, which is fabricated on [[TSMC]]'s [[16 nm process]], incorporates eight {{armh|Cortex-A53|l=arch}} cores with four [[little cores]] operating at up to 1.65 GHz and four [[big cores]] operating at up to 2.3 GHz. The Helio P23 supports up to 6 GiB of dual-channel LPDDR4X-3200 memory and incorporates a modem supporting [[LTE]] User Equipment (UE) category 6 and 7 (DL)/13 (UL). | ||
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{{unknown features}} | {{unknown features}} | ||
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| + | == Cache == | ||
| + | {{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}} | ||
| + | {{cache size}} | ||
| + | {{empty section}} | ||
| + | |||
| + | == Memory controller == | ||
| + | {{memory controller | ||
| + | |type=LPDDR4X-3200 | ||
| + | |type 2=LPDDR3-1866 | ||
| + | |ecc=No | ||
| + | |max mem=6 GiB | ||
| + | |controllers=1 | ||
| + | |channels=2 | ||
| + | |width=32 bit | ||
| + | |max bandwidth=23.84 GiB/s | ||
| + | |bandwidth schan=11.92 GiB/s | ||
| + | |bandwidth dchan=23.84 GiB/s | ||
| + | }} | ||
Revision as of 13:38, 10 September 2017
Template:mpu Helio P23 is a mid-range performance 64-bit octa-core ARM LTE system on a chip designed by MediaTek set to launch in late 2017. This SoC, which is fabricated on TSMC's 16 nm process, incorporates eight Cortex-A53 cores with four little cores operating at up to 1.65 GHz and four big cores operating at up to 2.3 GHz. The Helio P23 supports up to 6 GiB of dual-channel LPDDR4X-3200 memory and incorporates a modem supporting LTE User Equipment (UE) category 6 and 7 (DL)/13 (UL).
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Cortex-A53 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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This section is empty; you can help add the missing info by editing this page. |
Memory controller
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Integrated Memory Controller
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Facts about "Helio P23 (MT6763V/MT6763T) - MediaTek"
| has ecc memory support | false + |
| max memory bandwidth | 23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) + |
| max memory channels | 2 + |
| supported memory type | LPDDR4X-3200 + and LPDDR3-1866 + |