Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/core i3/i3-8100"
| Line 9: | Line 9: | ||
|part number=BX80684I38100 | |part number=BX80684I38100 | ||
|part number 2=BXC80684I38100 | |part number 2=BXC80684I38100 | ||
| + | |part number 3=CM8068403377308 | ||
|s-spec=SR3N5 | |s-spec=SR3N5 | ||
|market=Desktop | |market=Desktop | ||
| Line 16: | Line 17: | ||
|frequency=3,600 MHz | |frequency=3,600 MHz | ||
|bus type=DMI 3.0 | |bus type=DMI 3.0 | ||
| + | |bus links=4 | ||
|bus rate=8 GT/s | |bus rate=8 GT/s | ||
|clock multiplier=36 | |clock multiplier=36 | ||
| Line 24: | Line 26: | ||
|core name=Coffee Lake S | |core name=Coffee Lake S | ||
|core family=6 | |core family=6 | ||
| + | |core stepping=B0 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
| Line 36: | Line 39: | ||
|tstorage min=-25 °C | |tstorage min=-25 °C | ||
|tstorage max=125 °C | |tstorage max=125 °C | ||
| + | |package module 1={{packages/intel/lga-1151}} | ||
}} | }} | ||
'''Core i3-8100''' is a {{arch|64}} [[quad-core]] low-end performance [[x86]] desktop microprocessor set to be introduced by [[Intel]] in mid-[[2017]]. This chip, which is based on the {{intel|Coffee Lake|l=arch}} microarchitecture, is fabricated on Intel's 3rd generation [[14 nm|14 nm++ process]]. This processor, which has a base frequency of 3.6 GHz with a TDP of 65 Watts, supports up to 64 GiB of dual-channel DDR4-2400. | '''Core i3-8100''' is a {{arch|64}} [[quad-core]] low-end performance [[x86]] desktop microprocessor set to be introduced by [[Intel]] in mid-[[2017]]. This chip, which is based on the {{intel|Coffee Lake|l=arch}} microarchitecture, is fabricated on Intel's 3rd generation [[14 nm|14 nm++ process]]. This processor, which has a base frequency of 3.6 GHz with a TDP of 65 Watts, supports up to 64 GiB of dual-channel DDR4-2400. | ||
Revision as of 17:15, 10 September 2017
Template:mpu Core i3-8100 is a 64-bit quad-core low-end performance x86 desktop microprocessor set to be introduced by Intel in mid-2017. This chip, which is based on the Coffee Lake microarchitecture, is fabricated on Intel's 3rd generation 14 nm++ process. This processor, which has a base frequency of 3.6 GHz with a TDP of 65 Watts, supports up to 64 GiB of dual-channel DDR4-2400.
 |
Leaked Info! Some of the information presented in this article is solely based on leaks that were published online or obtained directly by WikiChip. It goes without saying that this information could change, be incomplete, wrong, or even made up. It's highly advised to wait for an official product announcement. |
 |
Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Coffee Lake § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||
Memory controller
 |
Integrated Memory Controller
|
|||||||||||||
|
||||||||||||||
Expansions
 |
Expansion Options
|
|||||||
|
||||||||
Graphics
 |
This section is empty; you can help add the missing info by editing this page. |
Features
[Edit/Modify Supported Features]
Facts about "Core i3-8100 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i3-8100 - Intel#io + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has ecc memory support | false + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology + |
| has intel enhanced speedstep technology | true + |
| has intel identity protection technology support | true + |
| has intel secure key technology | true + |
| has intel supervisor mode execution protection | true + |
| has second level address translation support | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
| max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| supported memory type | DDR3L-1600 + and DDR4-2400 + |
| x86/has memory protection extensions | true + |
| x86/has software guard extensions | true + |