From WikiChip
Difference between revisions of "renesas/r-car/v2h"
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+ | == Development Board ("BLANCHE") == | ||
+ | * 210 mm x 160 mm | ||
+ | * R-Car V2H | ||
+ | * 64 MiB NOR & 4 MiB SPI flash memory | ||
+ | * 1 GB DDR3-DRAM-1600; 32-bit configuration | ||
+ | * 6 x video inputs | ||
+ | * EtherAVB (GMII/MII) | ||
+ | * SD card host interfaces | ||
+ | * Two CAN interfaces | ||
+ | * HDMI and RGB display-out | ||
+ | * switches, LEDs, I/O expansion headers | ||
+ | * JTAG debug/trace connectors | ||
+ | * expansion connectors | ||
+ | * Five-channel low-delay H.264/JPEG decoder | ||
+ | * Image recognition engines |
Revision as of 05:19, 23 July 2017
Template:mpu R-Car V2H is high-performance embedded 64-bit dual-core arm SoC designed by Renesas for the automotive industry and introduced in 2014. The V2H has two Cortex-A15 cores operating at 1 GHz and incorporates the Imagination PowerVR SGX531 GPU. This SoC supports up to DDR3-1600 memory.
Samples for the V2H were available starting September 2014 with Renesas expecting mass production to begin around October 2016 with combined production reaching a volume of 500,000 units per month by October 2017.
Contents
Cache
- Main article: Cortex-A15 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
- Flash ROM and SRAM Data bus width: 8/16 bit
- CAN 2 channels
- Ethernet AVB; 1000 Mbps, 100 Mbps, IEEE802.3 PHY
Graphics
Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Development Board ("BLANCHE")
- 210 mm x 160 mm
- R-Car V2H
- 64 MiB NOR & 4 MiB SPI flash memory
- 1 GB DDR3-DRAM-1600; 32-bit configuration
- 6 x video inputs
- EtherAVB (GMII/MII)
- SD card host interfaces
- Two CAN interfaces
- HDMI and RGB display-out
- switches, LEDs, I/O expansion headers
- JTAG debug/trace connectors
- expansion connectors
- Five-channel low-delay H.264/JPEG decoder
- Image recognition engines
Facts about "R-Car V2H - Renesas"
has ecc memory support | true + |
integrated gpu | PowerVR SGX531 + |
integrated gpu designer | Imagination Technologies + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
max memory bandwidth | 5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR3-1600 + |